A voltage-frequency island aware energy optimization framework for networks-on-chip

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Volumn 1, Issue 3, 2011, Pages 420-432

  Jang, Wooyoung ^a   Pan, David Z ^b  

^a SAMSUNG Electronics   (South Korea)

^b The University of Texas at Austin   (United States)

Author keywords

Network on chip (NoC); system on chip (SoC); voltage frequency island (VFI)

Indexed keywords

ENERGY EFFICIENT; ENERGY OPTIMIZATION; FREQUENCY ASSIGNMENTS; GLOBAL ENERGY; INSERTION ALGORITHMS; MESH NETWORK; NETWORK ON CHIP; NETWORKS ON CHIPS; OPTIMIZATION FRAMEWORK; OUTPUT BUFFER; PERFORMANCE CONSTRAINTS; POWER-PERFORMANCE TRADE-OFFS; ROUTING PATH; SYSTEM-ON-CHIP (SOC); VOLTAGE LEVELS; VOLTAGE-FREQUENCY ISLANDS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; NETWORK ROUTING; OPTIMIZATION; PROGRAMMABLE LOGIC CONTROLLERS; VLSI CIRCUITS;

ENERGY EFFICIENCY;

EID: 81255171394     PISSN: 21563357     EISSN: None     Source Type: Journal    
DOI: 10.1109/JETCAS.2011.2165756     Document Type: Article

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