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Volumn , Issue , 2010, Pages 277-283

Clustering-based simultaneous task and voltage scheduling for NoC systems

Author keywords

[No Author keywords available]

Indexed keywords

CLUSTERING ALGORITHMS; COMPUTER AIDED DESIGN; ENERGY EFFICIENCY; VOLTAGE SCALING;

EID: 78650857336     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2010.5654180     Document Type: Conference Paper
Times cited : (11)

References (21)
  • 8
    • 34547308089 scopus 로고    scopus 로고
    • Statistical, leakage power minimization, using fast equi-slack shell based optimization
    • X. Ye, Y. Zhan, and P. Li. Statistical, leakage power minimization, using fast equi-slack shell based optimization. In Pmceedings of the 44th annual Design Automation Conference, pages 853-858, 2007.
    • (2007) Pmceedings of the 44th Annual Design Automation Conference , pp. 853-858
    • Ye, X.1    Zhan, Y.2    Li, P.3
  • 10
    • 0025415048 scopus 로고
    • Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
    • T. Sakurai and A.R. Newton. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. In IEEE Journal of Solid-State Circuits, 25 (2), pages 584-594, 1990.
    • (1990) IEEE Journal of Solid-State Circuits , vol.25 , Issue.2 , pp. 584-594
    • Sakurai, T.1    Newton, A.R.2
  • 12
    • 77956196661 scopus 로고    scopus 로고
    • ACES: Application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip
    • J. Cong, C. Liu, and G Reinman. ACES: Application-Specific Cycle Elimination and Splitting for Deadlock-Free Routing on Irregular Network-on-Chip. In Proceedings of Design Automation Conference, pages 443-448, 2010.
    • (2010) Proceedings of Design Automation Conference , pp. 443-448
    • Cong, J.1    Liu, C.2    Reinman, G.3
  • 14
    • 0032685389 scopus 로고    scopus 로고
    • Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
    • C. Chen, CCN. Chu, and D.F. Wong. Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian relaxation. In IEEE Transactions on Computer Aided Design, 18(7), page 1014-1025, 1999.
    • (1999) IEEE Transactions on Computer Aided Design , vol.18 , Issue.7 , pp. 1014-1025
    • Chen, C.1    Chu, C.C.N.2    Wong, D.F.3
  • 19
    • 51549106356 scopus 로고    scopus 로고
    • ELIAD: Efficient lithography aware detailed router with compact post-OPC printability prediction
    • M. Cho, Y. Kun, Yongchan Ban, and D.Z Pan. ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction. In Proceedings of Design Automation Conference, pages 504-509, 2008.
    • (2008) Proceedings of Design Automation Conference , pp. 504-509
    • Cho, M.1    Kun, Y.2    Ban, Y.3    Pan, D.Z.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.