An SDRAM-aware router for networks-on-chip

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 10, 2010, Pages 1572-1585

  Jang, Wooyoung ^a   Pan, David Z ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Flow control; memory; networks on chip; router; scheduler

Indexed keywords

COST-EFFICIENT; DATA CONTENTION; FLOW CONTROLLERS; GUARANTEED QUALITY; HARDWARE COST; MEMORY; MEMORY BANDWIDTHS; MEMORY EFFICIENCY; MEMORY LATENCIES; MEMORY PERFORMANCE; MEMORY SUBSYSTEMS; MULTI-STAGE; NETWORKS ON CHIPS; NOC DESIGN; PERFORMANCE BOTTLENECKS; PRIORITY-BASED; SCHEDULER; SCHEDULING SCHEMES; SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORIES; SYSTEMS ON CHIPS; TURN-AROUNDS;

DYNAMIC RANDOM ACCESS STORAGE; FLOW CONTROL; FORMAL METHODS; MICROPROCESSOR CHIPS; SCHEDULING;

ROUTERS;

EID: 77957000547     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2061251     Document Type: Article

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