NoC topology synthesis for supporting shutdown of voltage islands in SoCs

Proceedings - Design Automation Conference

Volumn , Issue , 2009, Pages 822-825

  Seiculescu, Ciprian ^a   Murali, Srinivasan ^a,b   Benini, Luca ^c   De Micheli, Giovanni ^a  

^a EPFL   (Switzerland)

^b INoCs   (Switzerland)

^c UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Leakage power; NoC; Shutdown; Topology; Voltage islands

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC POWER UTILIZATION; TOPOLOGY;

APPLICATION-SPECIFIC NETWORK; INTERCONNECT ARCHITECTURES; LEAKAGE POWER; LEAKAGE POWER CONSUMPTION; SHUTDOWN; SYSTEMS ON CHIPS; TOPOLOGY SYNTHESIS; VOLTAGE ISLAND;

NETWORK-ON-CHIP;

EID: 70350710310     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1629911.1630121     Document Type: Conference Paper

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