An SDRAM-aware router for networks-on-chip

Proceedings - Design Automation Conference

Volumn , Issue , 2009, Pages 800-805

  Jang, Wooyoung ^a   Pan, David Z ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Flow control; Memory; Networks on chip; Router

Indexed keywords

COMPUTER AIDED DESIGN; DATA STORAGE EQUIPMENT; DYNAMIC RANDOM ACCESS STORAGE; FLOW CONTROL; MEMORY ARCHITECTURE; ROUTERS;

GATE COUNT; HARDWARE COST; MEMORY LATENCIES; MEMORY SUBSYSTEMS; MEMORY UTILIZATION; NETWORKS ON CHIPS; PRIORITY-BASED; SCHEDULING SCHEMES;

NETWORK-ON-CHIP;

EID: 70350738624     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1629911.1630117     Document Type: Conference Paper

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