A voltage-frequency island aware energy optimization framework for networks-on-chip

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2008, Pages 264-269

  Wooyoung, Jang ^a   Duo, Ding ^a   Pan, David Z ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; CONFORMAL MAPPING; ELECTRIC NETWORK TOPOLOGY; ENERGY EFFICIENCY; GRAPHIC METHODS; OPTIMIZATION; WIRELESS TELECOMMUNICATION SYSTEMS;

ART WORKS; ENERGY CONSUMPTIONS; ENERGY OPTIMIZATIONS; ENERGY-EFFICIENT; FREQUENCY ASSIGNMENTS; MESH NETWORKS; NETWORKS ON CHIPS; ROUTING OPTIMIZATIONS; VOLTAGE LEVELS;

COMPUTER NETWORKS;

EID: 57849106351     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681584     Document Type: Conference Paper

References (18)

1. International Technology Roadmap for Semiconductors, 2006.
2. D. Wingard, "Micronetwork-based integration, for SoCs" In Proc. Design Automation Conf., 2001.
3. Luca Benini and Giovanni De Micheli, "Network on chips: a new SoC paradigm," Computer, 2002, 35, pp. 70-78.
4. William J. Dally and Brian Towles, "Route packets, not wires: on-chip interconnection, networks," In Proc. Design Automation Conf., 2001.
5. Jingcao Hu and Radu Marculescu, "Energy-aware mapping for tile-based NoC architectures under performance constraints," In Proc. Asian and South Pacific Design Automation Conference, 2003.
6. Jingcao Hu and Radu Marculescu, "Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures," In Proc. Design, Automation & Test in Europe, 2003.
7. Srinivasan Murali and Giovanni. De Micheli, "Bandwidth-constrained mapping of cores onto NoC architecture," In Proc. DATE'04.
8. C. J. Class and L. M. Ni, "The turn model for adaptive routing," J. ACM, vol. 41, no. 5, pp. 874-902, Sept. 1994.
9. Ge-Ming Chiu, "The odd-even turn model for adaptive routing," IEEE Trans. Parallel and Distributed Systems, vol. 11, no. 7, pp. 729-738, July 2000.
10. Umit Y. Ogras, Radu Marcuescu, Puru Choudhary and Diana Marculescu, "Voltage-frequency island partitioning for GALS-based networks-on-chip, " In Proc. Design Automation Conf., 2007.
11. Koushik Niyogi and Diana Marculescu, "Speed and voltage selection for GALS systems based on voltage/frequency islands," In Proc. Asian and South Pacific Design Automation Conference, 2005.
12. J. Hu, Y. Shin, N. Dhanwada, and R. Marculescu, "Architecting voltage islands in core-based system-on-a-chip designs. In Proc. ISLPED'04.
13. EB.Van Der Tol, EGT. Jaspers, "Mapping of MPEG-4 decoding on flexible architecture platform," SPIE 2002, pp. 1-13, Jan. 2002.
14. Robert P. Dick, "Embedded system synthesis benchmarks suites", http://www.ece.northwestern.edu/~dickrp.
15. S. Martin, K. Flautner, T. Mudge and D. Blaauw, "Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads," In Proc. ICCAD'02.
16. T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE Journal of Solid-State Circuits, 25(2), pp. 584-594, Apr. 1990.
17. J. A. Butts and G.S. Sohi, "A static power model for architects,' In Proc. Intl. Symp. of Microarchitecture, Dec. 2000.
18. J. Hu and R. Marculescu, "Communication and task scheduling of application-specific networks-on-chips," In IEE Proc. Comuters & Digital Techniques, pp. 643-651, Sep. 2006.