Application-aware NoC design for efficient SDRAM access

Proceedings - Design Automation Conference

Volumn , Issue , 2010, Pages 453-456

  Jang, Wooyoung ^a   Pan, David Z ^a  

^a The University of Texas at Austin   (United States)

Author keywords

Flow control; Memory; NoC; On chip communication; QoS; Router

Indexed keywords

APPLICATION-AWARE NETWORK; FLOW CONTROLLERS; MEMORY; MEMORY LATENCIES; MEMORY PERFORMANCE; MEMORY UTILIZATION; NOC; NOC DESIGN; ON CHIP COMMUNICATION; QOS; SHORT PACKETS;

COMPUTER AIDED DESIGN; DYNAMIC RANDOM ACCESS STORAGE; FLOW CONTROL; MICROPROCESSOR CHIPS;

ROUTERS;

EID: 77956200889     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1837274.1837387     Document Type: Conference Paper

References (12)

1. W. Jang and D. Z. Pan, "An SDRAM-aware router for networks-onchip," Proc. Design Automation Conference, 2009.
2. K. Goossens, J. Dielissen and A. Rǎdulescu, " Æthereal network on chip: concepts, architectures and implementations," IEEE Design and Test of Computers, vol.22, no.5, pp. 414-421, Sep. 2005.
3. M. Millberg, E. Nilsson, R. Thid and A. Jantsch, "Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip," Proc. DATE, 2004.
4. T. Bjerregaard and J. Sparso, "A router architecture for connectionoriented service guarantees in the MANGO clockless network-on-chip," Proc. Design, Automation and Test in Europe, 2005.
5. Y.-C. Lan, S.-H. Lo, Y.-C. Lin, Y.-H. Hu and S.-J. Chen, "BiNoC: a bidirectional NoC architecture with dynamic self-reconfigurable channel," Proc. International Symposium on Networks on chip, 2009.
6. "Device operations & timing diagram," Samsung Electronics, http://www.samsung.com/global/business/semiconductor.
7. T. Wiegand, G. J. Sullivan, G. Bjontegaard and A. Luthra, "Overview of the H.264/AVC video coding standard," IEEE Trans. on Circuits and System for Video Technology, vol.13, no.7, July 2003.
8. Open Core Protocol Specification, Release 2.0, 2003, http://www.ocpip. org.
9. "AMBA open specifications," ARM, http://www.arm.com.
10. "MemMax Scheduler," Sonics Inc., http://www.sonicsinc.com.
11. "Databahn DRAM Memory Controller IP," Denali Software Inc., http://www.denali.com.
12. W. Jang and D. Z. Pan, "A3MAP: Architecture-Aware Analytic Mapping for Networks-on-Chip," Proc. ASPDAC, 2010.