Energy-aware synthesis of networks-on-chip implemented with voltage islands

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 128-131

  Leung, Lap Fai ^a   Tsui, Chi Ying ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Network on chip; Routing; Voltage island

Indexed keywords

CALCULATIONS; COMMUNICATION; ELECTRIC POTENTIAL; ENERGY UTILIZATION; GENETIC ALGORITHMS; LARGE SCALE SYSTEMS; MICROPROCESSOR CHIPS; OPTIMIZATION; REAL TIME SYSTEMS;

BENCHMARKS; NETWORK-ON-CHIP; ROUTING; VOLTAGE ISLANDS;

NETWORKS (CIRCUITS);

EID: 34547316480     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375138     Document Type: Conference Paper

References (14)

1. W. J. Dally, B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," in Proc. of DAC, 2001
2. H. Wu et. al., "Post-placement voltage island generation under performance requirement," in Proc. of ICCAD, pp.309-316, 2005
3. Niyogi, K. and Marculescu, D., " Speed and voltage selection for GALS systems based on voltage/frequency island," in Proc. of ASPDAC, pp. 292-297, 2005
4. J. Hu et al., "Architecting voltage islands in core-based system-on-a-chip designs," in Proc. of ISLPED pp. 180-185, 2004
5. D. Shin and J. Kim, "Power-Aware Communication Optimization for Networks-On-Chips With Voltage Scalable Links," in Proc. of International Workshop on Hardware/Software Codesign, 2004
6. J. Hu, R. Marculescu, "Energy- and Performance Aware Mapping for Regular NoC Architectures,"IEEE Trans. On CAD, April, 2003
7. Cesar Marcon et al., "Time and Energy Efficient Mapping of Embedded Applications onto NoCs,".ASP-DAC, Jan 2005
8. F. Gruian, K. Kuchcinski, "LEneS: Task Scheduling for Low-energy Systems Using Variable Supply Voltage Processors," in Proc. of ASP-DAC, 2001
9. R. Dick. Embedded system synthesis benchmarks suites (E3S)
10. Kim, N. et al., "Visual Assessment of a Real-time System Design: A Case Study on a CNC Controller," in Proc. of RTSS, 1996
11. Cesar Marcon et al., "Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique," in Proc. of DATE, pp. 502-507, 2005
12. S. Murali and G. De Micheli, "Bandwidth-constrained mapping of cores onto NoC architectures," in Proc. DATE, pp. 16-20, Feb. 2004
13. I. Oliver, D. Smith, and J. Holland," A Study of Permutation Crossover Operations on the Traveling Salesman Problem," In Proc. International Conference on Genetic Algorithm, pages 224-230, 1987
14. Andrei, A., Schmitz, M. T., Eles, P., Peng, Z. and Al-Hashimi, B. M. (2004) Simultaneous Communication and Processor Voltage Scaling for Dynamic and Leakage Energy Reduction in Time-Constrained Systems. In Proceedings of International Conference on Computer-Aided Design, pp. 361-367, San Jose, USA.