GALS systems prototyping using multiclock FPGAS and asynchroinous network-on-chips

Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL

Volumn 2005, Issue , 2005, Pages 299-304

  Quartana, Jérôme ^a,b   Renane, Salim ^a   Baixas, Arnaud ^a   Fesquet, Laurent ^a   Renaudin, Marc ^a  

^a TIMA LABORATORY   (France)

^b ECOLE DES MINES DE SAINT ETIENNE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COSTS; LOGIC DESIGN; MICROPROCESSOR CHIPS; PRODUCT DESIGN; SCHEMATIC DIAGRAMS; TELECOMMUNICATION LINKS;

ASYNCHRONOUS NETWORK-ON-CHIP (ANOC); GLOBALLY-ASYNCHRONOUS LOCALLY-SYNCHRONOUS (GALS); MEMORY BANKS; NETWORK-ON-CHIPS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33746924544     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2005.1515738     Document Type: Conference Paper

References (23)

1. F. K. Gürkaynak, S. Oetiker, N. Felber, H. Kaeslin et W. Fichtner, "Is there hope for GALS in the future ?" Proc. of the 4th Asynchronous Circuit Design Workshop (ACID 2004), Turku, Finland, June 28-29, 2004.
2. J. B. Rigaud, J. Quartana, L. Fesquet et M. Renaudin, "Modeling and design of asynchronous priority arbiters for on-chip communication systems", Proc. of the VLSI-SOC'01, 11th IFIP Int. Conf. on Very Large Scale Integration, Montpellier, France, 3-5 Dec. 2001.
3. E. Beigné, F. Clermidy, P. Vivet, A. Clouard, M. Renaudin, "An Asynchronous NOC Architecture Providing Low Latency Service and its Multi-Level Design Flow", 11th IEEE Int. Symp. on Asynchronous Circuits and Systems (ASYNC'05), March 14-16, NY, USA, pp. 54-63, 2005.
4. W. J. Bainbridge et S. Furber, "CHAIN: A Delay Insensitive CHip Area INterconnect", IEEE Micro, vol. 22, no. 5, pp. 16-23, September/October 2002.
5. W. O. Lovett, "CHip Area Network Simulation", Master of Science, University of Manchester, 2002.
6. T. Villiger, H. Kaeslin, F. Gurkaynak, S. Oetiker et W. Fichtner, "Self-timed Ring for Globally-Asynchronous Locally-Synchronous Systems", Proc. of the Ninth Int. Symp.on Advanced Research in Asynchronous Circuits and Systems, ASYNC'03, Vancouver, Canada, May, 12-16 2003.
7. N. Huot, H. Dubreuil, L. Fesquet and M. Renaudin, "A FPGA Architecture for Multi-style Asynchronous Logic", Design Automation and Test in Europe (DATE), Germany, March 2005.
8. T. Q. Ho, J. B. Rigaud, M. Renaudin, L. Fesquet et R. Rolland, "Implementing Asynchronous Circuits on LUT Based FPGAs", Proc. of the Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th Int.Conference, FPL 2002, Montpellier, France, September 2-4, 2002.
9. M. Najibi, K. Saleh, M. Naderi, H. Pedram, M. Sedighi, "Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs", Proc. of the 2005 ACM/SIGDA 13th Int.Symp.on Field-programmable gate arrays, Monterey, California, USA, 2005.
10. C. Piguet, M. Renaudin, T. Omnés, "Low-power systems on chips (SOCs)", Proc. of the Conf.on Design, Automation, and Test in Europe, Munich, Germany, 2001.
11. Y. Semiat et R. Ginosar, "Timing Measurements of Synchronization Circuits", Proc. of the Ninth Int.Symp.on Advanced Research in Asynchronous Circuits and Systems, ASYNC'03, Vancouver, Canada, May, 12-16 2003.
12. A.J. Martin, "Programming in VLSI: from communicating processes to delay-insensitive circuits", in C.A.R. Hoare, Developments in Concurrency and Communication, UT Year of Programming Series, 1990, Addison-Wesley, p. 1-64.
13. Anh Vu Dinh Duc, Laurent Fesquet, Marc Renaudin, "Synthesis of QDI Asynchronous Circuits from DTL-style Petri-Net", IWLS-02, 11th IEEE/ACM Int.Workshop on Logic & Synthesis, New Orleans, Louisiana, June 4-7, 2002.
14. A.V. Dinh Duc, J.B. Rigaud, A. Rezzag, A. Sirianni, J. Fragoso, L. Fesquet, M. Renaudin, "TAST CAD Tools: Tutorial", tutorial given at the Int Symp. on Advanced Research in Asynchronous Circuits and Systems ASYNC'02, Manchester, UK, April 8-11, 2002,
15. and at the ACiD Summer School on "Asynchronous circuits design", Grenoble, France, July 15-19, 2002. TIMA internal report ISRN:TIMA-RR-02/07/01 - FR, http://tima.imag.fr/cis.
16. Ph. Maurine, J.B. Rigaud, F. Bouesse, G. Sicard, M. Renaudin, "Static Implementation of QDI asynchronous primitives", PATMOS'03 - 13th Int. Workshop on Power and Timing Modeling, Optimization and Simulation. Torino, Italy, September 10-12, 2003.
17. R. Ginosar, "Synchronization and Arbitration", Proc. of the ACiD Summer School on Asynchronous Circuit Design, Grenoble, France, July 15-19 2002.
18. R. Ginosar, "Fourteen ways to fool your Synchronizer", Proc. of the Ninth Int.Symp.on Research in Asynchronous Circuits and Systems, ASYNC'03, Vancouver, Canada, 2003.
19. J. Quartana, K. Slimani, M. Renaudin, "Asynchronous FIFO for Efficient and Reliable Synch/Asynch Interfaces in GALS Architectures", VLSI-SOC'05, submitted.
20. T. Chelcea et S. M. Nowick, "Robust Interfaces for Mixed-Timing Systems", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 8, pp. 2004.
21. R. Ho, J. Gainsley et R. Drost, "Long wires and asynchronous control", Proc. of the Asynch'04, 2004.
22. A. Bystrov, D. J. Kinniment, A. Yakovlev, "Priority Arbiters", in Int.Symp.on Advanced Research in Asynchronous Circuits and Systems (ASYNC'00), Eilat, Israel, April 2000, pp. 128-137.
23. F. Karim, A. Nguyen et S. Dey, "An Interconnect Architecture for Networking Systems on Chips", IEEE Micro, vol. 22, no. 5, pp. 36-45, September/October 2002.