Timing-constrained and voltage-island-aware voltage assignment

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 429-432

  Wu, Huaizhi ^a   Wong, Martin D F ^b   Liu, I Min ^c  

^a CADENCE DESIGN SYSTEMS   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^c Atoptech Inc ^*  (United States)

Author keywords

Low power; Timing; Voltage assignment; Voronoi diagram

Indexed keywords

ALGORITHMS; CONSTRAINED OPTIMIZATION; ELECTRIC POWER UTILIZATION; TIMING CIRCUITS; VOLTAGE CONTROL;

LOW POWER; SUPPLY VOLTAGES; VOLTAGE ASSIGNMENTS; VORONOI DIAGRAM;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 34250765870     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147023     Document Type: Conference Paper

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