Post-placement voltage island generation

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 641-646

  Ching, Royce L S ^a   Young, Evangeline F Y ^a   Leung, Kevin C K ^a   Chu, Chris ^b  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b IOWA STATE UNIVERSITY   (United States)

Author keywords

Floorplanning; Tree; Voltage island

Indexed keywords

DESIGN; ELECTRIC POWER UTILIZATION; HAND HELD COMPUTERS; NETWORKS (CIRCUITS); SULFATE MINERALS;

BATTERY LIFE; COMPUTER-AIDED DESIGN; DATA SETS; DYNAMIC POWER CONSUMPTION; EXPERIMENTAL RESULTS; HAND-HELD DEVICES; HIGH POWER CONSUMPTION; INTERNATIONAL CONFERENCES; ONE WAY; PARTITIONING PROBLEMS; PERFORMANCE TRADE-OFF; PHYSICAL SPACE; POWER CONSUMPTION (CE); REGION-BASED; RELIABILITY PROBLEMS; SOLUTION QUALITY; SUPPLY VOLTAGES; VOLTAGE ISLANDS;

LANDFORMS;

EID: 46149092789     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320028     Document Type: Conference Paper

References (6)

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3. J. Hu, Y. Shin, N. Dhanwada, and R. Marculescu. Architecting Voltage Islands in Core-based System-on-a-chip Designs. Proceedings of the 2004 International Symposiwm on Low Power Electronics and Design, pages 180-185, 2004.
4. D. E. Lackey, P. S. Zuchowski, T. R. Bednar, D. W. Stout, S. W. Gould, and J. M. Cohn. Managing Power and Performance for System-on-chip Designs using Voltage Islands. Proceedings IEEE International Conference on Computer-Aided Design, pages 195-202, 2002.
5. S. Muthukrishnan and T. Suel. Approximation Algorithms for Array Partitioning Problem. J. of Algorithms, 54:85-104, 2005.
6. H. Wu, I.-M. Liu, Martin D. F. Wong, and Y. Wang. Post-Placement Voltage Island Generation under Performance Requirement. Proceedings of the International Conference on Computer-Aided Design, 2005.