Computer-aided analog circuit design for reliability in nanometer CMOS

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Volumn 1, Issue 1, 2011, Pages 50-58

  Maricau, Elie ^a   Gielen, Georges ^a  

^a Katholieke Universiteit Leuven   (Belgium)

Author keywords

Bias temperature instability (BTI); circuit reliability analysis; design of experiments (DoE); hot carrier (HC); soft breakdown; variability aware simulation

Indexed keywords

BIAS TEMPERATURE INSTABILITY; CIRCUIT RELIABILITY ANALYSIS; DESIGN OF EXPERIMENTS (DOE); SOFT BREAKDOWN; VARIABILITY-AWARE SIMULATION;

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DESIGN; DESIGN OF EXPERIMENTS; ELECTRIC NETWORK ANALYSIS; FORTH (PROGRAMMING LANGUAGE); HOT CARRIERS; INTEGRATED CIRCUIT MANUFACTURE; RELIABILITY ANALYSIS;

ANALOG CIRCUITS;

EID: 79957852551     PISSN: 21563357     EISSN: None     Source Type: Journal    
DOI: 10.1109/JETCAS.2011.2135470     Document Type: Article

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