NBTI model for analogue IC reliability simulation

Electronics Letters

Volumn 46, Issue 18, 2010, Pages 1279-1280

  Maricau, E ^a   Gielen, G ^a  

^a Katholieke Universiteit Leuven   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURACY IMPROVEMENT; ANALOGUE CIRCUITS; CMOS PROCESSS; CMOS TECHNOLOGY; COMPACT MODEL; IC RELIABILITY; NANOMETRES; NEGATIVE BIAS TEMPERATURE INSTABILITY; PHYSICS-BASED MODELS; RELIABILITY SIMULATION; TIME VARYING; VOLTAGE STRESS;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; QUALITY ASSURANCE;

RELIABILITY ANALYSIS;

EID: 77956302706     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el.2010.1971     Document Type: Article

References (5)

1. 'International Technology Roadmap for Semiconductors (ITRS)', http://www.itrs.net/Links/2009ITRS/Home2009.htm, 2009
2. Grasser, T., and Kaczer, B.: ' Evidence that two tightly coupled mechanisms are responsible for negative bias instability in oxynitride MOSFETs ', IEEE Trans. Electron. Devices, 2009, 56, (5), p. 1056-1062 0018-9383
3. Kaczer, B., Grasser, T., and Roussel, R.: et al. ' Ubiquitous relaxation in BTI stressing - new evaluation and insights ', IEEE Int. Symp. on Reliability Physics, Phoenix, AZ, USA, 2008, p. 20-27
4. Parthasarathy, C.: ' Etude de la fiabilite des technologies CMOS avancees ', 2006, PhD, Universite d'Aix-Marseille
5. Alam, M.A., Kufluoglu, H., and Varghesc, S.: et al. ' A comprehensive model for PMOS NBTI degradation: recent progress ', Microelectron. Reliab., 2007, 47, (6), p. 853-862