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Volumn , Issue , 2009, Pages 1238-1241

Efficient reliability simulation of analog ICs including variability and time-varying stress

Author keywords

[No Author keywords available]

Indexed keywords

RELIABILITY; TIMING CIRCUITS;

EID: 70350068400     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090853     Document Type: Conference Paper
Times cited : (22)

References (10)
  • 1
    • 70350043284 scopus 로고    scopus 로고
    • Critical Reliability Challenges for the ITRS
    • Int. Sematech, Tech. Rep
    • "Critical Reliability Challenges for the ITRS," Int. Sematech, Tech. Rep., 2007.
    • (2007)
  • 2
    • 49749094341 scopus 로고    scopus 로고
    • Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies
    • G. Gielen et al, "Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies," DATE, 2008.
    • (2008) DATE
    • Gielen, G.1
  • 3
    • 34548677068 scopus 로고    scopus 로고
    • Statistical analysis during the reliability simulation
    • C. Bestory et al, "Statistical analysis during the reliability simulation," Microelectronics Reliability, 2007.
    • (2007) Microelectronics Reliability
    • Bestory, C.1
  • 4
    • 33748106481 scopus 로고    scopus 로고
    • A New SPICE Reliability Simulation Method for Deep Submicron CMOS VLSI Circuits
    • X. Li et al, "A New SPICE Reliability Simulation Method for Deep Submicron CMOS VLSI Circuits," TDMR, 2006.
    • (2006) TDMR
    • Li, X.1
  • 5
    • 77953091590 scopus 로고    scopus 로고
    • X. Xuan et al, IC reliability simulator ARET and its application in design-for-reliability, ATS, 2003.
    • X. Xuan et al, "IC reliability simulator ARET and its application in design-for-reliability," ATS, 2003.
  • 6
    • 50249178553 scopus 로고    scopus 로고
    • An Analytical Model for Hot Carrier Degradation in Nanoscale CMOS Suitable for the Simulation of Degradation in Analog IC Applications
    • E. Maricau, P. De Wit, and G. Gielen, "An Analytical Model for Hot Carrier Degradation in Nanoscale CMOS Suitable for the Simulation of Degradation in Analog IC Applications," Microelectronics Reliability, 2008.
    • (2008) Microelectronics Reliability
    • Maricau, E.1    De Wit, P.2    Gielen, G.3
  • 7
    • 19044394081 scopus 로고    scopus 로고
    • A geometrical unification of the theories of NBTI and HCI time-exponents and its implications for ultra-scaled planar and surround-gate MOSFETs
    • H. Kufluoglu and M. Alam, "A geometrical unification of the theories of NBTI and HCI time-exponents and its implications for ultra-scaled planar and surround-gate MOSFETs," IEDM, 2004.
    • (2004) IEDM
    • Kufluoglu, H.1    Alam, M.2
  • 8
    • 70350041448 scopus 로고    scopus 로고
    • Etude de la fiabilite des technologies cmos avancees
    • Ph.D. dissertation, Universite d'Aix-Marseille
    • C. Parthasarathy, "Etude de la fiabilite des technologies cmos avancees," Ph.D. dissertation, Universite d'Aix-Marseille, 2006.
    • (2006)
    • Parthasarathy, C.1
  • 9
    • 46049120673 scopus 로고    scopus 로고
    • AC NBTI studied in the 1 Hz-2 GHz range on dedicated on-chip CMOS circuits
    • R. Fernandez et al, "AC NBTI studied in the 1 Hz-2 GHz range on dedicated on-chip CMOS circuits," IEDM, 2006.
    • (2006) IEDM
    • Fernandez, R.1
  • 10
    • 70350066041 scopus 로고    scopus 로고
    • Reliability Simulation of Analog ICs under Time-Varying Stress in Nanoscale CMOS
    • E. Maricau et al, "Reliability Simulation of Analog ICs under Time-Varying Stress in Nanoscale CMOS," ITC DRVW, 2008.
    • (2008) ITC DRVW
    • Maricau, E.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.