Analytical yield prediction considering leakage/performance correlation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 9, 2006, Pages 1685-1695

  Rao, Rajeev R ^a,b   Devgan, Anirudh ^a,c   Blaauw, David ^a,b   Sylvester, Dennis ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

^c MAGMA DESIGN AUTOMATION   (United States)

Author keywords

Estimation; Leakage current; Parametric yield; Simulation

Indexed keywords

GATE LEAKAGE CURRENTS; LEAKAGE CURRENT DISTRIBUTION; PARAMETRIC YIELD; POWER LIMITS;

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; CONSTRAINT THEORY; CORRELATION THEORY; ESTIMATION; MICROPROCESSOR CHIPS; STATISTICAL METHODS;

LEAKAGE CURRENTS;

EID: 33748113950     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.858351     Document Type: Article

References (29)

1. J. Kao, S. Narendra, and A. Chandrakasan, "Subthreshold leakage modeling and reduction techniques," in Proc. ICCAD, San Jose, CA, Nov. 2002, pp. 141-148.
2. S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, no. 4, pp. 23-29, Jul./Aug. 1999.
3. K. Bernstein, C.-T. Chuang, R. Joshi, and R. Puri, "Design and CAD challenges in sub-90 nm CMOS technologies," in Proc. ICCAD, San Jose, CA, Nov. 2003, pp. 129-136.
4. S. Mukhopadhyay and K. Roy, "Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation," in Proc. ISLPED, Seoul, Korea, Aug. 2003, pp. 172-175.
5. Berkeley Predictive Technology Model (BPTM). [Online]. Available: http://www-device.eecs.berkeley.edu/~ptm/
6. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variations and impact on circuits and microarchitecture," in Proc. IEEE/ACM DAC, Anaheim, CA, Jun. 2003, pp. 338-342.
7. S. Narendra, V. De, S. Borkar, D. Antoniadis, and A. Chandrakasan, "Full-chip subthreshold leakage power prediction model for sub-0.1 μm CMOS," in Proc. ISLPED, Monterey, CA, Aug. 2002, pp. 19-23.
8. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, "Accurate estimate of total leakage current in scaled CMOS circuits based on compact current modeling," in Proc. IEEE/ACM DAC, Anaheim, CA, Jun. 2003, pp. 169-174.
9. R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, "Statistical analysis of subthreshold leakage current for CMOS circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 2, pp. 131-139, Feb. 2004.
10. A. Srivastava, R. Bai, D. Blaauw, and D. Sylvester, "Modeling and analysis of leakage power considering within-die process variations," in Proc. ISLPED, Monterey, CA, Aug. 2002, pp. 64-67.
11. F. Najm and N. Menezes, "Statistical timing analysis based on a timing yield model," in Proc. IEEE/ACM DAC, San Diego, CA, Jun. 2004, pp. 460-465.
12. S. Choi, B. Paul, and K. Roy, "Novel sizing algorithm for yield improvement under process variation in nanometer technology," in Proc. IEEE/ACM DAC, San Diego, CA, Jun. 2004, pp. 454-459.
13. S. Zhang, V. Wason, and K. Banerjee, "A probabilistic framework to estimate full-chip subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations," in Proc. ISLPED, Newport Beach, CA, Aug. 2004, pp. 156-161.
14. Y.-F. Tsai, D. Duarte, N. Vijaykrishnan, and M. J. Irwin, "Impact of process scaling on the efficacy of leakage reduction schemes," in Int. Conf. Integrated Circuit Design Technology (ICICDT), Austin, TX, May 2004, pp. 3-11.
15. BSIM4. [Online]. Available: http://www-device.eecs.berkeley.edu/ -bsim3/bsim4.html
16. S. Nassif, "Modeling and forecasting of manufacturing variations," in Int. Workshop Statistical Metrology, Honolulu, HI, Jun. 2000, pp. 2-10.
17. A. Papoulis, Probability, Random Variables and Stochastic Processes. New York: McGraw-Hill, 1991.
18. B. Cory, R. Kapur, and B. Underwood, "Speed binning with path delay test in 150-nm technology," IEEE Des. Test Comput., vol. 20, no. 5, pp. 41-45, Oct. 2003.
19. A. Keshavarzi, K. Roy, C. Hawkins, and V. De, "Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 5, pp. 863-870, Oct. 2003.
20. K. Bowman, S. Duvall, and J. Meindl, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 183-190, Feb. 2002.
21. A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, "Computation and refinement of statistical bounds on circuit delay," in Proc, IEEE/ACM DAC, Anaheim, CA, Jun. 2003, pp. 348-353.
22. M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu, "Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 21, no. 5, pp. 544-553, May 2002.
23. S. Samaan, "The impact of device parameter variations on the frequency and performance of VLSI chips," in Proc. IEEE/ACM ICCAD, San Jose, CA, Nov. 2004, pp. 343-346.
24. K. Bowman, S. Samaan, and N. Hakim, "Maximum clock frequency distribution model with practical VLSI design considerations," in Int. Conf. Integrated Circuit Design Technology (ICICDT), Austin, TX, May 2004, pp. 183-191.
25. International Technology Roadmap for Semiconductors (ITRS). (2001). [Online]. Available, http://public.itrs.net
26. N. C. Beaulieu, A. A. Abu-Dayya, and P. J. Mclane, "Estimating the distribution of a sum of independent log-normal random variables," IEEE Trans. Commun., vol. 43, no. 12, pp. 2869-2873, Dec. 1995.
27. R. Rao, A. Devgan, D. Blaauw, and D. Sylvester, "Parametric yield estimation considering leakage variability," in Proc. IEEE/ACM DAC, San Diego, CA, Jun. 2004, pp. 442-447.
28. Log Normal Distribution. [Online], Available: http://mathworld. wolfram.com/LogNormalDistribution.html
29. Maple 9.5. [Online], Available: http://www.maplesoft.com/products/ maple/