An analytical model for hot carrier degradation in nanoscale CMOS suitable for the simulation of degradation in analog IC applications

Microelectronics Reliability

Volumn 48, Issue 8-9, 2008, Pages 1576-1580

  Maricau, E ^a   De Wit, P ^a   Gielen, G ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITS; CIVIL AVIATION; DEGRADATION; EPITAXIAL GROWTH; HOT CARRIERS; MOSFET DEVICES; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; PROCESS DESIGN; PROCESS ENGINEERING; THRESHOLD VOLTAGE; UNMANNED AERIAL VEHICLES (UAV);

65NM CMOS TECHNOLOGY; ANALOG IC; ANALYTICAL MODELLING; CHANNEL HOT CARRIER; HOT-CARRIER DEGRADATION; NANO-SCALE CMOS; NANO-SCALE TRANSISTORS; OUTPUT CONDUCTANCE; PROCESS PARAMETERS; STRESS CONDITIONS; THRESHOLD-VOLTAGE DEGRADATION; TRANSISTOR DEGRADATION; TRANSISTOR PARAMETERS; TRANSISTOR PERFORMANCE;

SULFATE MINERALS;

EID: 50249178553     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2008.06.016     Document Type: Article

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