Designing dependable multicore system with unreliable components

2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009

Volumn , Issue , 2009, Pages 154-

  Chandra, Vikas ^a  

^a ARM R and D ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE DESIGNS; DYNAMIC VARIATIONS; MOORE'S LAW; MULTI-CORE SYSTEMS; NANOSCALE ERA; SINGLE CORE CHIPS;

EID: 70449455881     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2009.5195999     Document Type: Conference Paper

References (3)

1. S. Borkar, "Thousand Core Chips-A Technology Perspective," DAC, 2007.
2. S. Das et al, "A Self-Tuning DVS Processor using Delay-Error Detection and Correction," IEEE JSSC, pp. 792-804, Apr. 2006.
3. Y. Li et al, "CASP: concurrent autonomous chip self-test using stored test patterns," DATE, 2008.