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Volumn , Issue , 2011, Pages 746-751

Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL ISSUES; DYNAMIC DATA; DYNAMIC ENERGY; DYNAMIC ENERGY CONSUMPTION; ENERGY EFFICIENT; HIGH DENSITY; LEAKAGE ENERGIES; LEAKAGE POWER; LEAKAGE POWER CONSUMPTION; LOW-POWER CONSUMPTION; MEMORY ACCESS TIME; NON-VOLATILE MEMORIES; ON CHIP MEMORY; ON CHIPS; SCRATCH PAD MEMORY; SMALL AREA; SUBMICRON; TECHNOLOGY SCALING;

EID: 79957545701     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (93)

References (34)
  • 1
    • 0036045884 scopus 로고    scopus 로고
    • Scratchpad memory: Design alternative for cache on-chip memory in embedded systems
    • R. Banakar, S. Steinke, B.-S. Lee, M. Balakrishnan, and P. Marwedel, "Scratchpad memory: design alternative for cache on-chip memory in embedded systems," in CODES '02, 2002, pp. 73-78.
    • (2002) CODES '02 , pp. 73-78
    • Banakar, R.1    Steinke, S.2    Lee, B.-S.3    Balakrishnan, M.4    Marwedel, P.5
  • 2
    • 70350066513 scopus 로고    scopus 로고
    • Power and performance of read-write aware hybrid caches with non-volatile memories
    • X. Wu, J. Li, L. Zhang, E. Speight, and Y. Xie, "Power and performance of read-write aware hybrid caches with non-volatile memories," in DATE '09, 2009, pp. 737-742.
    • (2009) DATE '09 , pp. 737-742
    • Wu, X.1    Li, J.2    Zhang, L.3    Speight, E.4    Xie, Y.5
  • 4
    • 51549109199 scopus 로고    scopus 로고
    • Circuit and microarchitecture evaluation of 3d stacking magnetic ram (mram) as a universal memory replacement
    • X. Dong, X. Wu, G. Sun, Y. Xie, H. Li, and Y. Chen, "Circuit and microarchitecture evaluation of 3d stacking magnetic ram (mram) as a universal memory replacement," in DAC '08, 2008, pp. 554-559.
    • (2008) DAC '08 , pp. 554-559
    • Dong, X.1    Wu, X.2    Sun, G.3    Xie, Y.4    Li, H.5    Chen, Y.6
  • 5
    • 70450243083 scopus 로고    scopus 로고
    • Hybrid cache architecture with disparate memory technologies
    • X. Wu, J. Li, L. Zhang, E. Speight, R. Rajamony, and Y. Xie, "Hybrid cache architecture with disparate memory technologies," in ISCA '09, 2009, pp. 34-45.
    • (2009) ISCA '09 , pp. 34-45
    • Wu, X.1    Li, J.2    Zhang, L.3    Speight, E.4    Rajamony, R.5    Xie, Y.6
  • 6
    • 77953117822 scopus 로고    scopus 로고
    • Energy- and endurance-aware design of phase change memory caches
    • Y. Joo, D. Niu, X. Dong, G. Sun, N. Chang, , and Y. Xie, "Energy- and endurance-aware design of phase change memory caches," in DATE '10, 2010, pp. 136-141.
    • (2010) DATE '10 , pp. 136-141
    • Joo, Y.1    Niu, D.2    Dong, X.3    Sun, G.4    Chang, N.5    Xie, Y.6
  • 7
    • 84872094294 scopus 로고    scopus 로고
    • An optimal memory allocation scheme for scratch-pad-based embedded systems
    • O. Avissar, R. Barua, and D. Stewart, "An optimal memory allocation scheme for scratch-pad-based embedded systems," ACM Trans. Embed. Comput. Syst., vol. 1, no. 1, pp. 6-26, 2002.
    • (2002) ACM Trans. Embed. Comput. Syst. , vol.1 , Issue.1 , pp. 6-26
    • Avissar, O.1    Barua, R.2    Stewart, D.3
  • 8
    • 18844371462 scopus 로고    scopus 로고
    • Compiler-decided dynamic memory allocation for scratch-pad based embedded systems
    • S. Udayakumaran and R. Barua, "Compiler-decided dynamic memory allocation for scratch-pad based embedded systems," in CASES '03, 2003, pp. 276-286.
    • (2003) CASES '03 , pp. 276-286
    • Udayakumaran, S.1    Barua, R.2
  • 9
    • 33746039960 scopus 로고    scopus 로고
    • Heap data allocation to scratch-pad memory in embedded systems
    • A. Dominguez, S. Udayakumaran, and R. Barua, "Heap data allocation to scratch-pad memory in embedded systems," J. Embedded Comput., vol. 1, no. 4, pp. 521-540, 2005.
    • (2005) J. Embedded Comput. , vol.1 , Issue.4 , pp. 521-540
    • Dominguez, A.1    Udayakumaran, S.2    Barua, R.3
  • 10
    • 47649086892 scopus 로고    scopus 로고
    • Dynamic allocation for scratch-pad memory using compile-time decisions
    • S. Udayakumaran, A. Dominguez, and R. Barua, "Dynamic allocation for scratch-pad memory using compile-time decisions," ACM Trans. Embed. Comput. Syst., vol. 5, no. 2, pp. 472-511, 2006.
    • (2006) ACM Trans. Embed. Comput. Syst. , vol.5 , Issue.2 , pp. 472-511
    • Udayakumaran, S.1    Dominguez, A.2    Barua, R.3
  • 12
    • 84886733545 scopus 로고    scopus 로고
    • Shared scratch-pad memory space management
    • O. Ozturk, M. Kandemir, and I. Kolcu, "Shared scratch-pad memory space management," in ISQED '06, 2006, pp. 576-584.
    • (2006) ISQED '06 , pp. 576-584
    • Ozturk, O.1    Kandemir, M.2    Kolcu, I.3
  • 13
    • 34047150455 scopus 로고    scopus 로고
    • Dynamic scratch-pad memory management for irregular array access patterns
    • G. Chen, O. Ozturk, M. Kandemir, and M. Karakoy, "Dynamic scratch-pad memory management for irregular array access patterns," in DATE '06, 2006, pp. 931-936.
    • (2006) DATE '06 , pp. 931-936
    • Chen, G.1    Ozturk, O.2    Kandemir, M.3    Karakoy, M.4
  • 14
    • 34047222785 scopus 로고    scopus 로고
    • Spm conscious loop scheduling for embedded chip multiprocessors
    • L. Xue, M. Kandemir, G. Chen, and T. Yemliha, "Spm conscious loop scheduling for embedded chip multiprocessors," in ICPADS '06, 2006, pp. 391-400.
    • (2006) ICPADS '06 , pp. 391-400
    • Xue, L.1    Kandemir, M.2    Chen, G.3    Yemliha, T.4
  • 15
    • 49749084020 scopus 로고    scopus 로고
    • A scratch-pad memory aware dynamic loop scheduling algorithm
    • O. Ozturk, M. Kandemir, and S. H. K. Narayanan, "A scratch-pad memory aware dynamic loop scheduling algorithm," in ISQED '08, 2008, pp. 738-743.
    • (2008) ISQED '08 , pp. 738-743
    • Ozturk, O.1    Kandemir, M.2    Narayanan, S.H.K.3
  • 16
    • 0030686025 scopus 로고    scopus 로고
    • Efficient utilization of scratch-pad memory in embedded processor applications
    • P. R. Panda, N. D. Dutt, and A. Nicolau, "Efficient utilization of scratch-pad memory in embedded processor applications," in EDTC '97, 1997, p. 7.
    • (1997) EDTC '97 , pp. 7
    • Panda, P.R.1    Dutt, N.D.2    Nicolau, A.3
  • 17
    • 77953097582 scopus 로고    scopus 로고
    • Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems
    • H. Takase, H. Tomiyama, and H. Takada, "Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems," in DATE '10, 2010, pp. 1124-1129.
    • (2010) DATE '10 , pp. 1124-1129
    • Takase, H.1    Tomiyama, H.2    Takada, H.3
  • 18
    • 84893786147 scopus 로고    scopus 로고
    • Assigning program and data objects to scratchpad for energy reduction
    • S. Steinke, L. Wehmeyer, B. Lee, and P. Marwedel, "Assigning program and data objects to scratchpad for energy reduction," in DATE '02, 2002, p. 409.
    • (2002) DATE '02 , pp. 409
    • Steinke, S.1    Wehmeyer, L.2    Lee, B.3    Marwedel, P.4
  • 19
    • 16244366467 scopus 로고    scopus 로고
    • Banked scratch-pad memory management for reducing leakage energy consumption
    • IEEE Computer Society
    • M. Kandemir, M. J. Irwin, G. Chen, and I. Kolcu, "Banked scratch-pad memory management for reducing leakage energy consumption," in ICCAD '04. IEEE Computer Society, 2004, pp. 120-124.
    • (2004) ICCAD '04 , pp. 120-124
    • Kandemir, M.1    Irwin, M.J.2    Chen, G.3    Kolcu, I.4
  • 20
    • 28444441683 scopus 로고    scopus 로고
    • Dataflow analysis for energy-efficient scratch-pad memory management
    • G. Chen and M. Kandemir, "Dataflow analysis for energy-efficient scratch-pad memory management," in ISLPED '05, 2005, pp. 327-330.
    • (2005) ISLPED '05 , pp. 327-330
    • Chen, G.1    Kandemir, M.2
  • 21
    • 70450277571 scopus 로고    scopus 로고
    • A durable and energy efficient main memory using phase change memory technology
    • P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "A durable and energy efficient main memory using phase change memory technology," in ISCA '09, 2009.
    • (2009) ISCA '09
    • Zhou, P.1    Zhao, B.2    Yang, J.3    Zhang, Y.4
  • 22
    • 70350714582 scopus 로고    scopus 로고
    • Pdram: A hybrid pram and dram main memory system
    • G. Dhiman, R. Ayoub, and T. Rosing, "Pdram: a hybrid pram and dram main memory system," in DAC '09, 2009, pp. 664-469.
    • (2009) DAC '09 , pp. 664-1469
    • Dhiman, G.1    Ayoub, R.2    Rosing, T.3
  • 23
    • 70450273507 scopus 로고    scopus 로고
    • Scalable high performance main memory system using phase-change memory technology
    • M. K. Qureshi, V. Srinivasan, and J. A. Rivers, "Scalable high performance main memory system using phase-change memory technology," in ISCA '09, 2009, pp. 24-33.
    • (2009) ISCA '09 , pp. 24-33
    • Qureshi, M.K.1    Srinivasan, V.2    Rivers, J.A.3
  • 24
    • 77956207016 scopus 로고    scopus 로고
    • Reducing write activities on non-volatile memories in embedded cmps via data migration and recomputation
    • J. Hu, C. J. Xue, W.-C. Tseng, Y. He, M. Qiu, and E. H.-M. Sha, "Reducing write activities on non-volatile memories in embedded cmps via data migration and recomputation," in DAC '10, 2010, pp. 350-355.
    • (2010) DAC '10 , pp. 350-355
    • Hu, J.1    Xue, C.J.2    Tseng, W.-C.3    He, Y.4    Qiu, M.5    Sha, E.H.-M.6
  • 25
    • 77955734495 scopus 로고    scopus 로고
    • Minimizing write activities to non-volatile memory via scheduling and recomputation
    • J. Hu, C. J. Xue, W.-C. Tseng, Q. Zhuge, and E. H.-M. Sha, "Minimizing write activities to non-volatile memory via scheduling and recomputation," in SASP '10, 2010, pp. 7-12.
    • (2010) SASP '10 , pp. 7-12
    • Hu, J.1    Xue, C.J.2    Tseng, W.-C.3    Zhuge, Q.4    Sha, E.H.-M.5
  • 27
    • 77954496810 scopus 로고    scopus 로고
    • Write activity reduction on flash main memory via smart victim cache
    • L. Shi, C. J. Xue, J. Hu, W.-C. Tseng, and E. H.-M. Sha, "Write activity reduction on flash main memory via smart victim cache," in GLVLSI '10, 2010, pp. 91-94.
    • (2010) GLVLSI '10 , pp. 91-94
    • Shi, L.1    Xue, C.J.2    Hu, J.3    Tseng, W.-C.4    Sha, E.H.-M.5
  • 28
    • 78650950735 scopus 로고    scopus 로고
    • Optimal scheduling to minimize non-volatile memory access time with hardware cache
    • W.-C. Tseng, C. J. Xue, Q. Zhuge, J. Hu, and E. H.-M. Sha, "Optimal scheduling to minimize non-volatile memory access time with hardware cache," in VLSI-SOC '10, 2010, pp. 131-136.
    • (2010) VLSI-SOC '10 , pp. 131-136
    • Tseng, W.-C.1    Xue, C.J.2    Zhuge, Q.3    Hu, J.4    Sha, E.H.-M.5
  • 29
    • 77953118185 scopus 로고    scopus 로고
    • A nondestructive self-reference scheme for spin-transfer torque random access memory (stt-ram)
    • Y. Chen, H. Li, X. Wang, W. Zhu, W. Xu, and T. Zhang, "A nondestructive self-reference scheme for spin-transfer torque random access memory (stt-ram)," in DATE '10, 2010, pp. 148-153.
    • (2010) DATE '10 , pp. 148-153
    • Chen, Y.1    Li, H.2    Wang, X.3    Zhu, W.4    Xu, W.5    Zhang, T.6
  • 31
    • 84878310212 scopus 로고    scopus 로고
    • A 0.9v, 65nm logic-compatible embedded dram with >1ms data retention time and 53% less static power than a power-gated sram
    • K. C. Chun, P. Jain, and C. H. Kim, "A 0.9v, 65nm logic-compatible embedded dram with >1ms data retention time and 53% less static power than a power-gated sram," in ISLPED '09, 2009, pp. 119-120.
    • (2009) ISLPED '09 , pp. 119-120
    • Chun, K.C.1    Jain, P.2    Kim, C.H.3
  • 33
    • 76349091566 scopus 로고    scopus 로고
    • Pcramsim: System-level performance, energy, and area modeling for phase-change ram
    • X. Dong, N. P. Jouppi, and Y. Xie, "Pcramsim: System-level performance, energy, and area modeling for phase-change ram," in ICCAD '09, 2009, pp. 269-275.
    • (2009) ICCAD '09 , pp. 269-275
    • Dong, X.1    Jouppi, N.P.2    Xie, Y.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.