-
1
-
-
70350064236
-
-
http://hpl.hp.com/research/cacti/.
-
-
-
-
2
-
-
70350070514
-
-
Specjbb2005 (java server bencharmk). In http://www.spec.org/jbb2005.
-
Specjbb2005 (java server bencharmk). In http://www.spec.org/jbb2005.
-
-
-
-
3
-
-
70350072451
-
-
Standard Performance Evaluation Corporation
-
Standard Performance Evaluation Corporation. 2006.
-
(2006)
-
-
-
4
-
-
33751334352
-
Current status of chalcogenide phase change memory
-
G. Atwood and R. Bez. Current status of chalcogenide phase change memory. In Device Research Conference Digest, volume 1, pages 29-33, 2005.
-
(2005)
Device Research Conference Digest
, vol.1
, pp. 29-33
-
-
Atwood, G.1
Bez, R.2
-
5
-
-
33749079198
-
BioPerf: A benchmark suite to evaluate high-performance computer architecture on bioinformatics applications
-
D. A. Bader, Y. Li, T. Li, and V. Sachdeva. BioPerf: a benchmark suite to evaluate high-performance computer architecture on bioinformatics applications. In Proceedings of the 2005 IEEE international symposium on workload characterization, pages 163-173, 2005.
-
(2005)
Proceedings of the 2005 IEEE international symposium on workload characterization
, pp. 163-173
-
-
Bader, D.A.1
Li, Y.2
Li, T.3
Sachdeva, V.4
-
6
-
-
0003605996
-
The NAS parallel benchmarks
-
Technical report RNR-91-002 revision2
-
D. Bailey, J. Barton, T. Lasinski, and H. Simon. The NAS parallel benchmarks. In Technical report RNR-91-002 revision2, pages 453-464, 1991.
-
(1991)
, pp. 453-464
-
-
Bailey, D.1
Barton, J.2
Lasinski, T.3
Simon, H.4
-
7
-
-
21644472427
-
Managing wire delay in large chip-multiprocessor caches
-
B. M. Beckmann and D. A. Wood. Managing wire delay in large chip-multiprocessor caches. In MICRO, pages 319-330, 2004.
-
(2004)
MICRO
, pp. 319-330
-
-
Beckmann, B.M.1
Wood, D.A.2
-
9
-
-
27544432313
-
Optimizing replication, communication, and capacity allocation in CMPs
-
Z. Chishti, M. D. Powell, and T. N. Vijaykumar. Optimizing replication, communication, and capacity allocation in CMPs. SIGARCH Comput. Archit. News, 33(2):357-368, 2005.
-
(2005)
SIGARCH Comput. Archit. News
, vol.33
, Issue.2
, pp. 357-368
-
-
Chishti, Z.1
Powell, M.D.2
Vijaykumar, T.N.3
-
10
-
-
49049114935
-
Cell design considerations for phase change memory as a universal memory
-
L. Chung. Cell design considerations for phase change memory as a universal memory. In VLSI-TSA, pages 132-133, 2008.
-
(2008)
VLSI-TSA
, pp. 132-133
-
-
Chung, L.1
-
11
-
-
51549109199
-
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement
-
X. Dong, X. Wu, G. Sun, Y. Xie, H. Li, and Y. Chen. Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. In DAC, pages 554-559, 2008.
-
(2008)
DAC
, pp. 554-559
-
-
Dong, X.1
Wu, X.2
Sun, G.3
Xie, Y.4
Li, H.5
Chen, Y.6
-
12
-
-
33847743417
-
A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-ram
-
M. Hosomi, H. Yamagishi, T. Yamamoto, and et al. A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram. In International Electron Devices Meeting, pages 459-462, 2005.
-
(2005)
International Electron Devices Meeting
, pp. 459-462
-
-
Hosomi, M.1
Yamagishi, H.2
Yamamoto, T.3
and et, al.4
-
13
-
-
0036949388
-
An adaptive, nonuniform cache structure for wire-delay dominated on-chip caches
-
C. Kim, D. Burger, and S. W. Keckler. An adaptive, nonuniform cache structure for wire-delay dominated on-chip caches. In ASPLOS-X, pages 211-222, 2002.
-
(2002)
ASPLOS-X
, pp. 211-222
-
-
Kim, C.1
Burger, D.2
Keckler, S.W.3
-
14
-
-
0029179077
-
The SPLASH-2 programs: Characterization and methodological considerations
-
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 programs: characterization and methodological considerations. SIGARCH Comput. Archit. News, 23(2):24-36, 1995.
-
(1995)
SIGARCH Comput. Archit. News
, vol.23
, Issue.2
, pp. 24-36
-
-
Woo, S.C.1
Ohara, M.2
Torrie, E.3
Singh, J.P.4
Gupta, A.5
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