Increasing PCM main memory lifetime

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2010, Pages 914-919

  Ferreira, Alexandre P ^a   Zhou, Miao ^a   Bock, Santiago ^a   Childers, Bruce ^a   Melhem, Rami ^a   Mossé, Daniel ^a  

^a University of Pittsburgh   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE REPLACEMENT POLICY; ENERGY REDUCTION; FAILURE DETECTION; MAIN MEMORY; PHASE CHANGE MEMORY (PCM); WEAR LEVELING; WRITE ENDURANCES; WRITE-BACK;

PHASE CHANGE MEMORY;

EID: 77953091093     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2010.5456923     Document Type: Conference Paper

References (11)

1. N. AbouGhazaleh, B. Childers, D. Mossé, and R. Melhem, "Power management in external memory using PA-CDRAM," in The Int'l. Journal for Embedded Systems (IJES), vol. 3-1, 2007, pp. 65-72.
2. W. Zhang and T. Li, "Exploring phase change memory and 3D die-stacking for power/thermal friendly, fast and durable memory architectures," in Int'l. Conf. on Parallel Architectures and Compilation Techniques (PACT), 2009, pp. 101-112.
3. M. K. Qureshi, V. Srinivasan, and J. A. Rivers, "Scalable high performance main memory system using phase-change memory technology," in Int'l. Symp. on Computer Architecture (ISCA), 2009, pp. 24-33.
4. B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, "Architecting phase change memory as a scalable dram alternative," in Int'l. Symp. on Computer Architecture (ISCA), 2009, pp. 2-13.
5. P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "A durable and energy efficient main memory using phase change memory technology," in Int'l. Symp. on Computer Architecture (ISCA), 2009, pp. 14-23.
6. S. Raoux et al., "Phase-change random access memory: A scalable technology," in IBM Journal of Research and Development, vol. 52, no. 4, 2008, pp. 465-479.
7. S. Mylavarapu, S. Choudhuri, A. Shrivastava, J. Lee, and T. Givargis, "Fsaf: File system aware flash translation layer for nand flash memories," in DATE '09., April 2009, pp. 399-404.
8. K. Takeuchi, "Novel co-design of nand flash memory and nand flash controller circuits for sub-30 nm low-power high-speed solid-state drives (ssd)," Solid-State Circuits, IEEE Journal of, vol. 44, no. 4, pp. 1227-1234, April 2009.
9. "Process integration, devices and structures," in Int'l. Technology Roadmap for Semiconductors, 2007.
10. Lee, K. J. et al, "A 90 nm 1.8 v 512 mb diode-switch pram with 266 mb/s read throughput," Solid-State Circuits, IEEE Journal of, vol. 43, no. 1, pp. 150-162, Jan. 2008.
11. Kang et al, "A 0.1 μm 1.8V 256Mb 66MHz Synchronous Burst PRAM," in IEEE Int'l. Solid-State Circuits Conf. (ISSCC), 2006.