Write activity reduction on flash main memory via smart victim cache

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2010, Pages 91-94

  Shi, Liang ^a,b,c   Xue, Chun Jason ^b,c   Hu, Jingtong ^d   Tseng, Wei Che ^d   Zhou, Xuehai ^a,b   Sha, Edwin H M ^d  

^a UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA   (China)

^b University of Science and Technology of China   (China)

^c CITY UNIVERSITY OF HONG KONG   (Hong Kong)

^d The University of Texas at Dallas   (United States)

Author keywords

cache; main memory; nand flash memory; victim cache

Indexed keywords

CACHE ARCHITECTURE; COARSE GRAINS; LOW LEAKAGE POWER; MAIN MEMORY; NAND FLASH MEMORY; NONVOLATILITY; READ OPERATION; TRADITIONAL ARCHITECTURE; WRITE OPERATIONS;

CACHE MEMORY; EMBEDDED SYSTEMS; LAKES; NAND CIRCUITS;

FLASH MEMORY;

EID: 77954496810     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1785481.1785503     Document Type: Conference Paper

References (10)

1. Spec cpu2000 benchmarks. In http://www.spec.org/cpu/.
2. T. Austin, E. Larson, and D. Ernst. Simplescalar: an infrastructure for computer system modeling. Computer, 35(2):59-67, Feb 2002.
3. Y.-H. Chang, J.-W. Hsieh, and T.-W. Kuo. Endurance enhancement of flash-memory storage systems: an efficient static wear leveling design. In DAC '07: Proceedings of the 44th annual Design Automation Conference, pages 212-217, June 2007.
4. Y.-H. Chang and T.-W. Kuo. A commitment-based management strategy for the performance and reliability enhancement of flash-memory storage systems. In DAC '09: Proceedings of the 46th Annual Design Automation Conference, pages 858-863, July 2009.
5. S. Electronics. Ik9f8g08uxm 1g x 8bit nand flash memory data sheet. In SAMSUNG Electronics CO., LTD., Sep 2006.
6. N. P. Jouppi. Retrospective: improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In ISCA '98: 25 years of the international symposia on Computer architecture (selected papers), pages 71-73, June 1998.
7. S. Jung, J. H. Kim, and Y. H. Song. Hierarchical architecture of flash-based storage systems for high performance and durability. In DAC '09: Proceedings of the 46th Annual Design Automation Conference, pages 907-910, July 2009.
8. T. Kgil, D. Roberts, and T. Mudge. Improving nand flash based disk caches. In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture, pages 327-338, June 2008.
9. K. Lee and A. Orailoglu. Application specific non-volatile primary memory for embedded systems. In CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, pages 31-36, Oct 2008.
10. C. Park, J. Seo, S. Bae, H. Kim, S. Kim, and B. Kim. A low-cost memory architecture with nand xip for mobile embedded systems. In CODES+ISSS '03: Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pages 138-143, Oct 2003.