Optimal scheduling to minimize non-volatile memory access time with hardware cache

Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010

Volumn , Issue , 2010, Pages 131-136

  Tseng, Wei Che ^a   Xue, Chun Jason ^b   Zhuge, Qingfeng ^c   Hu, Jingtong ^a   Sha, Edwin H M ^a  

^a The University of Texas at Dallas   (United States)

^b CITY UNIVERSITY OF HONG KONG   (Hong Kong)

^c JIANGNAN UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

ILP FORMULATION; LIST-SCHEDULING; MAIN MEMORY; MAIN-MEMORY ACCESS; MEMORY ACCESS; NON-VOLATILE MEMORIES; OPTIMAL SCHEDULING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; EMBEDDED SYSTEMS; FLASH MEMORY; PHASE CHANGE MEMORY; PROGRAMMABLE LOGIC CONTROLLERS; SCHEDULING;

CACHE MEMORY;

EID: 78650950735     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2010.5642609     Document Type: Conference Paper

References (11)

1. M. Wu and W. Zwaenepoel, "envy: a non-volatile, main memory storage system," in ASPLOS-VI: Proceedings of the sixth international conference on Architectural support for programming languages and operating systems, San Jose, California, United States, 1994, pp. 86-97.
2. K. Lee and A. Orailoglu, "Application specific non-volatile primary memory for embedded systems," in CODES/ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, Atlanta, GA, USA, 2008, pp. 31-36.
3. "Onenand features and performance," 2007, [Online]. Available: http://www.samsung.com/global/business/semiconductor/products/ fusionmemory/Products OneNAND.html [Accessed: Sept. 10, 2009].
4. P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "A durable and energy efficient main memory using phase change memory technology," SIGARCH Comput. Archit. News, vol. 37, no. 3, pp. 14-23, 2009.
5. M. K. Qureshi, V. Srinivasan, and J. A. Rivers, "Scalable high performance main memory system using phase-change memory technology," in ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture, Austin, TX, USA, 2009, pp. 24-33.
6. I. Williams, "Phase change memory is another step closer," Oct. 2009, http://www.hpcwire.com/news/Phase-Change-Memory-is-Another-Step-Closer. html.
7. H.-T. Lue, E.-K. Lai, S.-Y. Wang, L.-W. Yang, T. Yang, K.-C. Chen, K.- Y. Hsieh, R. Liu, and C.-Y. Lu, "A novel gate-injection program/erase p-channel nand-type flash memory with high (10m cycle) endurance," in VLSI Technology, 2007 IEEE Symposium on, June 2007, pp. 140-141.
8. F. Yeung, S.-J. Ahn, Y.-N. Hwang, C.-W. Jeong, Y.-J. Song, S.-Y. Lee, S.-H. Lee, K.-C. Ryoo, J.-H. Park, J.-M. Shin, W.- C. Jeong, Y.-T. Kim, G.-H. Koh, G.-T. Jeong, H.-S. Jeong, and K. Kim, "Ge2sb2te5 confined structures and integration of 64mb phase-change random access memory," Japanese Journal of Applied Physics, vol. 44, no. 4B, pp. 2691-2695, 2005. [Online]. Available: http://jjap.ipap.jp/link?JJAP/44/2691/
9. V. Zivojnovic, J. Martinez, C. Schlager, and H. Meyr, "Dspstone: A dsporiented benchmarking methodology," in ICSPAT'94: In Proceedings of the International Conference on Signal Processing Applications and Technology, Dallas, Texas, USA, 1994.
10. R. Graham, "Bounds for certain multiprocessing anomalies," Bell System Technical Journal, vol. 45, pp. 1563-1581, 1966.
11. L. SYSTEMS, "Lingo 12.0 - optimization modeling software for linear, nonlinear, and integer programming," http://www.lindo.com/index.php.