Scratchpad memory: A design alternative for cache on-chip memory in embedded systems

Hardware/Software Codesign - Proceedings of the International Workshop

Volumn , Issue , 2002, Pages 73-78

  Banakar, Rajeshwari ^a   Steinke, Stefan ^a   Lee, Bo Sik ^a   Balakrishnan, M ^a   Marwedel, Peter ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CACHE MEMORY; COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DATA REDUCTION; MATHEMATICAL MODELS; PROGRAM COMPILERS;

AREA-TIME REDUCTION; CACHE ON CHIP MEMORY; CACHE SIZES; SCRATCHPAD MEMORY; TARGET PROCESSOR;

EMBEDDED SYSTEMS;

EID: 0036045884     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Embedded DRAM development technology, physical design, and application issues
2. DSPStone: A DSP-oriented benchmarking methodology
3. Cacti: An enhanced access and cycle time model
4. Comparison of cache and scratch pad based memory system with respect to performance, area and energy consumption
5. Low power design - Abstraction levels and RTL design techniques
6. Synthesis of application specific memories for power optimisation in embedded systems
7. The filter cache: An energy efficient memory structure
8. A power reduction technique with object code merging for application specific embedded processors