Independent-gate and tied-gate FinFET SRAM circuits: Design guidelines for reduced area and enhanced stability

Proceedings of the International Conference on Microelectronics, ICM

Volumn , Issue , 2007, Pages 171-174

  Tawfik, Sherif A ^a   Liu, Zhiyu ^a   Kursun, Volkan ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT OPERATIONS; CMOS TECHNOLOGIES; DESIGN GUIDELINES; DOUBLE GATES; ENHANCED STABILITIES; HIGH-PERFORMANCE MICROPROCESSORS; IDLE MODES; INTEGRATION DENSITIES; MEMORY ARRAYS; MINIMUM-SIZED TRANSISTORS; ON-CHIP CACHES; POWER CONSUMPTION; READ STABILITIES; SRAM CELLS; STANDBY MODES; STATIC RANDOM ACCESS MEMORIES;

CELLS; CMOS INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS; MICROELECTRONICS; STABILITY; TECHNOLOGY;

STATIC RANDOM ACCESS STORAGE;

EID: 51849160433     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICM.2007.4497686     Document Type: Conference Paper

References (11)

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