A gate-level strategy to design carry select adders

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2004, Pages

  Alioto, M ^a   Palumbo, G ^b   Poli, M ^b  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DIGITAL DEVICES; GATES (TRANSISTOR); MULTIPLEXING; OPTIMIZATION; PARAMETER ESTIMATION; SIGNAL PROCESSING;

CARRY SELECT ADDERS (CSA); FULL ADDER CHAINS; MULTIPLEXERS (MUX); RIPPLE CARRY ADDERS (RCA);

ADDERS;

EID: 4344561930     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. C. Nagendra, M. J. Irwin, M. Owens, "Area-Time-Power Tradeoffs in Parallel Adders," Trans. on CAS-part II, vol. 43, no. 10, pp. 689-702, Oct. 1996.
2. O. Bedrij, "Carry Select Adder," IRE Trans. on Electronic Computers, vol. EC-11, pp. 340-346, 1962.
3. Y. Huang, J. B. Kuo, "A High-Speed Conditional Carry Select (CCS) Adder Circuit with a Successively Incremented Carry Number Block (SICNB) Structure for Low-Voltage VLSI Implementation," IEEE Trans. on CAS - part II, vol. 47, no. 10, pp. 1074-1079, Oct. 2000.
4. M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sakai, Y. Nakagome, "A 1.5-ns 32-b CMOS ALU in Double Pass-Transistor Logic," IEEE J. Solid-State Circuits, vol. 28, pp. 1145-1150, Nov. 1993.
5. A. Tyagi, "A Reduced-Area Scheme for Carry-Select Adder," Trans. on Computers, vol. 42, no. 10, pp. 1163-1170, Oct. 1993.
6. B. Parhami, Computer Arithmetic, Algorithms and Hardware Designs, Oxford University Press, 2000.
7. nd Ed., Prentice-Hall, 2003.