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Volumn 25, Issue 4, 2004, Pages 199-201

High-performance P-type independent-gate FinFETs

Author keywords

Double gate (DG); FinFET; Independent gate (IG); MOSFET; Threshold tuning; Threshold voltage

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; GATES (TRANSISTOR); MOSFET DEVICES; SEMICONDUCTOR DEVICE MODELS; THRESHOLD VOLTAGE;

EID: 1942520273     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.825160     Document Type: Letter
Times cited : (39)

References (13)
  • 2
  • 3
    • 4243216494 scopus 로고    scopus 로고
    • High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices
    • J. Kedzierski, "High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices," in IEDM Tech. Dig., Dec. 2001, pp. 19.5.1-19.5.4.
    • IEDM Tech. Dig., Dec. 2001
    • Kedzierski, J.1
  • 5
    • 0036923594 scopus 로고    scopus 로고
    • Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation
    • J. Kedzierski, "Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation," in IEDM Tech. Dig., Dec. 2002, pp. 247-250.
    • IEDM Tech. Dig., Dec. 2002 , pp. 247-250
    • Kedzierski, J.1
  • 6
    • 0036923438 scopus 로고    scopus 로고
    • FinFET scaling to 10 nm gate length
    • B. Yu, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., Dec. 2002, pp. 251-254.
    • IEDM Tech. Dig., Dec. 2002 , pp. 251-254
    • Yu, B.1
  • 7
    • 0036923636 scopus 로고    scopus 로고
    • A functional FinFET-DGCMOS SRAM cell
    • E. Nowak, "A functional FinFET-DGCMOS SRAM cell," in IEDM Tech. Dig., Dec. 2002, pp. 411-414.
    • IEDM Tech. Dig., Dec. 2002 , pp. 411-414
    • Nowak, E.1
  • 8
    • 84886447996 scopus 로고    scopus 로고
    • Self-aligned (top and bottom) double-gate MOSFET with a 25-nm-thick silicon channel
    • H.-S. Wong, "Self-aligned (top and bottom) double-gate MOSFET with a 25-nm-thick silicon channel," in IEDM Tech. Dig., Dec. 1997, pp. 427-430.
    • IEDM Tech. Dig., Dec. 1997 , pp. 427-430
    • Wong, H.-S.1
  • 9
    • 10844274151 scopus 로고    scopus 로고
    • High performance double-gate device technology challenges and opportunities
    • M. Ieong, "High performance double-gate device technology challenges and opportunities," in Proc. Int. Symp. Quality Electronic Design, Mar. 2002, pp. 492-495.
    • Proc. Int. Symp. Quality Electronic Design, Mar. 2002 , pp. 492-495
    • Ieong, M.1
  • 10
    • 26144458297 scopus 로고    scopus 로고
    • Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOS-FETs
    • ____, "Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOS-FETs," in IEDM Tech. Dig., Dec. 2001, pp. 19.6.1-19.6.4.
    • IEDM Tech. Dig., Dec. 2001
    • Ieong, M.1
  • 12
    • 0141786921 scopus 로고    scopus 로고
    • Improved independent gate N-type FinFET fabrication and characterization
    • Sept.
    • ____, "Improved independent gate N-type FinFET fabrication and characterization," IEEE Electron Device Lett., vol. 24, pp. 592-595, Sept. 2003.
    • (2003) IEEE Electron Device Lett. , vol.24 , pp. 592-595
    • Fried, D.1
  • 13
    • 0034863489 scopus 로고    scopus 로고
    • Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design
    • R. Zhang, "Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design," in Proc. Int. Symp. Low-Power Electronics and Design, Aug. 2001, pp. 213-218.
    • Proc. Int. Symp. Low-Power Electronics and Design, Aug. 2001 , pp. 213-218
    • Zhang, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.