FinFET Technology for Future Microprocessors

IEEE International SOI Conference

Volumn , Issue , 2003, Pages 33-34

  Ludwig, T ^a   Aller, I ^a   Gernhoefer, V ^a   Keinert, J ^a   Nowak, E ^b   Joshi, R V ^c   Mueller, A ^a   Tomaschko, S ^a  

^a IBM   (Germany)

^b IBM MICROELECTRONICS   (United States)

^c IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SOFTWARE; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS; TOPOLOGY;

CIRCUIT DESIGN;

MICROPROCESSOR CHIPS;

EID: 0142217096     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/soi.2003.1242886     Document Type: Conference Paper

References (6)

1. H.-S. Wong, "Nanoscale CMOS", Proc. IEEE, Vol. 87, No.4, p.537, April 1999
2. D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda, "A Fully Depleted Lean-channel Transistor (DELTA) ", IEDM 1989, p. 833, 1989
3. S.-H. Tang et al., "FinFET-A quasi-planar Double-Gate MOSFET", ISSCC 2001, p.118, 2001
4. t asymmetric-gate FinFET devices", IEDM 2001, p.437, 2001
5. V. Gernhöfer, "FinGEN, a tool for automated FinFET level generation", unpublished
6. R. Williams and E. Nowak, "FinFET PowerSPICE compact model", unpublished