A new memory monitoring scheme for memory-aware scheduling and partitioning

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 2002-January, Issue , 2002, Pages 117-128

  Suh, G E ^a   Devadas, S ^a   Rudolph, L ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Analytical models; Computer architecture; Computer science; Computerized monitoring; Counting circuits; Hardware; Laboratories; Processor scheduling; Runtime; Yarn

Indexed keywords

ANALYTICAL MODELS; BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SCIENCE; COUNTING CIRCUITS; HARDWARE; LABORATORIES; MEMORY ARCHITECTURE; SCHEDULING; SUPERCOMPUTERS; YARN;

CACHE HITS; CACHE MISS RATES; LOW OVERHEAD; LRU REPLACEMENTS; MEMORY AWARE; NOVEL HARDWARE; PROCESSOR SCHEDULING; RUNTIMES;

CACHE MEMORY;

EID: 84949769332     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2002.995703     Document Type: Conference Paper

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