Turbo NOC: A framework for the design of network-on-chip-based turbo decoder architectures

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 57, Issue 10, 2010, Pages 2776-2789

  Martina, Maurizio ^a   Masera, Guido ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

Network on chip (NOC); turbo decoder; VLSI

Indexed keywords

COMPUTER ARCHITECTURE; DECODING; NETWORK ARCHITECTURE; NETWORK ROUTING; NETWORK-ON-CHIP; SERVERS; TOPOLOGY;

DESIGN AND SIMULATION; HIGH THROUGHPUT; NETWORK TOPOLOGY; NETWORK-ON-CHIP(NOC); PROCESSING NODES; ROUTING STRATEGIES; TURBO DECODERS; VLSI;

INTEGRATED CIRCUIT DESIGN;

EID: 77957933158     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2010.2046257     Document Type: Article

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