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Volumn 53, Issue 11, 2005, Pages 1833-1840

Variable-size interleaver design for parallel turbo decoder architectures

Author keywords

Parallel architecture; Prunable interleavers; S random interleavers

Indexed keywords

BLOCK CODES; COMPUTER SIMULATION; DECODING; ERROR ANALYSIS; PARALLEL ALGORITHMS; PROBABILITY; RANDOM PROCESSES; TURBO CODES;

EID: 28844496344     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCOMM.2005.858685     Document Type: Article
Times cited : (32)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.