Variable-size interleaver design for parallel turbo decoder architectures

GLOBECOM - IEEE Global Telecommunications Conference

Volumn 5, Issue , 2004, Pages 3108-3112

  Dinoi, Libero ^a   Benedetto, Sergio ^b  

^a ISTITUTO SUPERIORE MARIO BOELLA   (Italy)

^b POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; CHANNEL CAPACITY; COMPUTER SIMULATION; MOBILE TELECOMMUNICATION SYSTEMS; PHASE MODULATION; PHASE SHIFT KEYING; TURBO CODES; VECTORS;

INTERLEAVERS; PARALLEL TURBO DECODERS; PARALLELISM; SPATIAL PERMUTATIONS;

DECODING;

EID: 18144362071     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error-correcting coding and decoding: turbo codes", in Proc. IEEE Conf. Communications, vol. 2, Geneva, Switzerland, 1993, pp. 1064-1070.
2. D. Divsalar and F. Pollara, "Turbo codes for PCS applications", Proc. IEEE Conf. Communications, vol. 1, Seattle, Washington (USA), June 1995, pp. 54-59
3. S. N. Crozier, "New High-Spread High-Distance Interleavers for Turbo-Codes", Biennial Symposium on Communications, Kingston, Ontario (Canada), May 28-31, 2000, pp.3-7
4. L. Dinoi and S. Benedetto, "Design of Prunable S-random interleavers", Proc. 3rd International Symposium on Turbo Codes and Related Topics, Brest, France, 2003, pp. 279-282
5. A. Giulietti, L. Van der Perre, and M. Strum, "Parallel turbo coding interleavers: avoiding collisions in accesses to storage elements", Electronics Letters, Vol. 38, Iss. 5, Feb. 2002, pp. 232-234
6. S. Benedetto, D. Divsalar, G. Montorsi, and F. Pollara, "Soft-input soft-output modules for the construction and distributed iterative decoding of code networks", European transactions on telecommunications, Vol. 9, Iss. 2, Mar. 1998, pp.155-172
7. J. Kwak and K. Lee, "Design of dividable interleaver for parallel decoding in turbo codes", Electronics Letters, Vol. 38, Iss. 22, Oct. 2002, pp. 1362-1364
8. D. Gnaedig, E. Boutillon, M. Jezequel, V.C. Gaudet, and P.G. Gulak, "On Multiple Slice Turbo Codes", Proc. 3rd International Symposium on Turbo Codes and Related Topics, Brest, France, 2003, pp. 343-346
9. R. Dobkin, M. Peleg, and R. Ginosar, "Parallel VLSI architectures and Parallel Interleaving Design for Low-Latency MAP Turbo Decoders", Technical Report CCIT-TR436
10. A. Tarable, G. Montorsi, and S. Benedetto, "Mapping interleaving laws to parallel Turbo decoder architectures", Proc. 3rd International Symposium on Turbo Codes and Related Topics, Brest, France, 2003, pp. 153-156
11. M.J. Thul, F. Gilbert, and N. Wehn, "Optimized concurrent interleaving architecture for high-throughput turbo-decoding", 9th Int. Conf. On Electronics, Circuits and Systems 2002, vol. 3, pp. 1099-1102
12. Third Generation Partnership Project/Universal Mobile Telecommunication Systems, "Multiplexing and channel coding (FDD)", 3GTS 25.212, version 3.4.0 (release 2000), www.3gpp.org
13. R. Garello, P. Pierleoni, and S. Benedetto, "Computing the free distance of turbo codes and serially concatenated codes with interleavers: Algorithms and applications", IEEE Journal on Selected Areas in Communications, vol. 19, no. 5, pp. 800-812, May 2001
14. A. Hunt, S. Crozier, M. Richards, and K. Gracie, "Performance Degradation as a Function of Overlap Depth when using Sub-Block Processing in the Decoding of Turbo Codes", Proceedings of the 6th International Mobile Satellite Conference, Ottawa, Canada, June 16-18, 1999, pp. 276-280