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Volumn 12, Issue 11, 2008, Pages 846-848
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Hardware design of a low complexity, parallel interleaver for WiMax duo-binary turbo decoding
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Author keywords
Hardware; Parallel interleaver; VLSL
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Indexed keywords
ELECTRIC BATTERIES;
INTEROPERABILITY;
TURBO CODES;
BLOCK SIZES;
CLOCK FREQUENCIES;
HARDWARE DESIGNS;
INTERLEAVERS;
LOW COMPLEXITIES;
PARALLEL INTERLEAVER;
PROPOSED ARCHITECTURES;
REDUCED COMPLEXITIES;
STANDARD CELL TECHNOLOGIES;
TURBO DECODERS;
TURBO DECODING;
VLSL;
DECODING;
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EID: 57849119827
PISSN: 10897798
EISSN: None
Source Type: Journal
DOI: 10.1109/LCOMM.2008.081113 Document Type: Article |
Times cited : (8)
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References (7)
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