Optimized concurrent interleaving architecture for high-throughput HRBO-decoding

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 2002, Pages 1099-1102

  Thul, Michael J ^a   Gilbert, Frank ^a   Wehn, Norbert ^a  

^a Rheinland Pfälzische Technische Universität Kaiserslautern Landau   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

3RD GENERATION; COMPONENT DECODERS; DEEP SUB-MICRON TECHNOLOGY; DESIGN APPROACHES; FUTURE APPLICATIONS; GLOBAL CONTROL; GLOBAL ROUTING; HIGH THROUGHPUT; INTERLEAVERS; INTERLEAVING ARCHITECTURE; PARALLELIZATIONS; VHDL-MODEL; WIRELESS COMMUNICATIONS;

CONCURRENCY CONTROL; DATA TRANSFER; OPTIMIZATION; THROUGHPUT; TURBO CODES; WIRELESS TELECOMMUNICATION SYSTEMS;

DECODING;

EID: 77956428704     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2002.1046443     Document Type: Conference Paper

References (7)

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