From parallelism levels to a Multi-ASIP architecture for turbo decoding

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 1, 2009, Pages 92-102

  Muller, Olivier ^a   Baghdadi, Amer ^a   Jézéquel, Michel ^a  

^a TECHNOPÔLE BREST IROISE   (France)

Author keywords

Application specific instruction set processor (ASIP); Bahl Cocke Jelinek Raviv (BCJR); Multiprocessor; Parallel processing; Turbo decoding

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; APPLICATIONS; CODES (STANDARDS); COMPUTER SOFTWARE REUSABILITY; DATA STORAGE EQUIPMENT; DIGITAL COMMUNICATION SYSTEMS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PARALLEL PROCESSING SYSTEMS; PIPELINES; SIGNAL ENCODING; TURBO CODES; WIMAX (CANDIDATE);

APPLICATION-SPECIFIC INSTRUCTION-SET PROCESSOR (ASIP); BAHL-COCKE-JELINEK-RAVIV (BCJR); MULTIPROCESSOR; PARALLEL PROCESSING; TURBO DECODING;

DECODING;

EID: 58849124782     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2003164     Document Type: Article

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