Flexible architectures for LDPC decoders based on network on chip paradigm

12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009

Volumn , Issue , 2009, Pages 582-589

  Vacca, Fabrizio ^a   Masera, Guido ^a,b   Moussa, Hazem ^b   Baghdadi, Amer ^b   Jezequel, Michel ^b  

^a POLITECNICO DI TORINO   (Italy)

^b TECHNOPÔLE BREST IROISE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE AREA; BANDWIDTH LOSS; FLEXIBLE ARCHITECTURES; LDPC DECODER; LOW DENSITY PARITY CHECK; NETWORK ON CHIP;

DECODING; EMPLOYMENT;

MICROPROCESSOR CHIPS;

EID: 74549226214     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2009.235     Document Type: Conference Paper

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