Design of dividable interleaver for parallel decoding in turbo codes

Electronics Letters

Volumn 38, Issue 22, 2002, Pages 1362-1364

  Kwak, Jaeyoung ^a   Lee, Kwyro ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; DATA STORAGE EQUIPMENT; DECODING; ITERATIVE METHODS; PARALLEL PROCESSING SYSTEMS; PROBLEM SOLVING;

DIVIDABLE INTERLEAVERS;

TURBO CODES;

EID: 0037168148     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20020916     Document Type: Article

References (4)

1. Berrou, C., Glavieux, A., and Thitimajshima, P.: 'Near Shannon limit error-correcting coding and decoding: turbo-codes'. IEEE Int. Conf. on Communications, Geneva, Switzerland, May 1993, Vol. 2, pp. 1064-1070.
2. Schurgers, C., Catthoor, F., and Engels, M.: 'Optimized MAP turbo decoder'. IEEE Workshop on Signal Processing Systems, Lafayette, LA, USA, 2000, pp. 245-254.
3. Hsu, J.-M., and Wang, C.-L.: 'A parallel decoding scheme for turbo codes'. IEEE Int. Symp. on Circuits and Systems, Monterey, CA, USA, June 1998, Vol. 4, pp. 445-448.
4. Giulietti, A., Van Der Perre, L., and Strum, M.: 'Parallel turbo coding interleavers: avoiding collisions in accesses to storage elements.', Electron. Lett., 2002, 38, (5), pp. 232-234.