Parallel turbo coding interleavers: Avoiding collisions in accesses to storage elements

Electronics Letters

Volumn 38, Issue 5, 2002, Pages 232-234

  Giulietti, A ^a,b   Van Der Perre, L ^a   Strum, M ^b  

^a IMEC   (Belgium)

^b UNIVERSITY OF SÃO PAULO   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; COMPUTER SIMULATION; CONVOLUTIONAL CODES; DATA TRANSFER; DECODING;

CONVOLUTION TURBO DECODERS; TURBO CODING INTERLEAVERS;

TURBO CODES;

EID: 0037186099     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20020148     Document Type: Article

References (4)

1. Near Shannon limit error correcting coding and decoding: Turbo-codes
2. Memory optimization of MAP turbo decoder algorithms
3. On the design of prunable interleavers for turbo codes
4. Weight distributions for turbo codes using random and nonrandom permutations