Network-on-chip-centric approach to interleaving in high throughput channel decoders

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1766-1769

  Neeb, Christian ^a   Thul, Michael J ^a   Wehn, Norbert ^a  

^a University of Koblenz Landau   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPONENT DECODERS; DATA BLOCKS; DECODER ARCHITECTURE; EFFICIENT CHANNELS; HIGH THROUGHPUT; INTERLEAVERS; NETWORK ON CHIP; ON CHIPS; PARALLELIZATION; PERMUTATION PATTERNS; PRE-PROCESSING; RUNTIME; WIRELESS COMMUNICATIONS;

CHANNEL CODING; ELECTRIC NETWORK TOPOLOGY; THROUGHPUT; WIRELESS NETWORKS;

ITERATIVE DECODING;

EID: 33847238215     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464950     Document Type: Conference Paper

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