-
1
-
-
0032023656
-
-
European transactions on telecommunications, vol. ETT 9, March-April 1998
-
S. Benedetto, D. Divsalar, G. Montorsi, F. Pollara (1998) "Soft-input soft-output modules for the construction and distributed iterative decoding of code networks", European transactions on telecommunications, vol. ETT 9, March-April 1998
-
(1998)
Soft-input Soft-output Modules for the Construction and Distributed Iterative Decoding of Code Networks
-
-
Benedetto, S.1
Divsalar, D.2
Montorsi, G.3
Pollara, F.4
-
2
-
-
0034270950
-
New deterministic interleaver designs for turbo-codes
-
Sept. 2000
-
O. Y. Takeshita and D. J. Costello (2000) "New deterministic interleaver designs for turbo-codes", IEEE Trans Info. theory, IT-46, Sept. 2000, pp. 1988-2000
-
(2000)
IEEE Trans Info. Theory, IT-46
, pp. 1988-2000
-
-
Takeshita, O.Y.1
Costello, D.J.2
-
3
-
-
0016037512
-
Optimal decoding of linear codes for minimizing symbol error rate
-
March 1974
-
L.R. Bahl, J. Cocke, F. Jelinek, and J. Raviv (1974) "Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate", IEEE Transactions on Information Theory, March 1974, pp. 284-287.
-
(1974)
IEEE Transactions on Information Theory
, pp. 284-287
-
-
Bahl, L.R.1
Cocke, J.2
Jelinek, F.3
Raviv, J.4
-
4
-
-
0029699452
-
Soft-output decoding algorithms for continuous decoding of parallel concatenated convolutional codes
-
Dallas, Texas, June 1996
-
S. Benedetto, D. Divsalar, G. Montorsi, F. Pollara (1996) "Soft-output decoding algorithms for continuous decoding of parallel concatenated convolutional codes", Proceedings of ICC'96, Dallas, Texas, June 1996.
-
(1996)
Proceedings of ICC'96
-
-
Benedetto, S.1
Divsalar, D.2
Montorsi, G.3
Pollara, F.4
-
5
-
-
84890154419
-
-
www.etek.chalmers.se/groups/arithdb
-
-
-
-
6
-
-
0001862523
-
Soft input soft output MAP module to decode parallel and serial concatenated codes
-
Jet Propulsion Lab., Pasadena, CA, 1996
-
S. Benedetto, D. Divsalar, G. Montorsi, F. Pollara (1996) "Soft input soft output MAP module to decode parallel and serial concatenated codes", in TDA Progr. Rep. 42-127, Jet Propulsion Lab., Pasadena, CA, pp. 1-20, 1996.
-
(1996)
TDA Progr. Rep.
, vol.42
, Issue.127
, pp. 1-20
-
-
Benedetto, S.1
Divsalar, D.2
Montorsi, G.3
Pollara, F.4
-
8
-
-
0003085644
-
Efficient implementation of continuous MAP decoders and a synchronization technique for turbo decoders
-
Victoria, B.C., Canada, 1996
-
S. S. Pietrobon (1996) "Efficient implementation of continuous MAP decoders and a synchronization technique for turbo decoders", in Proc. Int. Symp. Inform. Theory Appl., Victoria, B.C., Canada, 1996, pp. 586-589.
-
(1996)
Proc. Int. Symp. Inform. Theory Appl
, pp. 586-589
-
-
Pietrobon, S.S.1
-
9
-
-
0029234412
-
A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain
-
1995
-
P. Robertson, E. Villebrun, P. Hoeher (1995) "A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain" Proc. ICC95, pp. 1009-1013, 1995.
-
(1995)
Proc. ICC95
, pp. 1009-1013
-
-
Robertson, P.1
Villebrun, E.2
Hoeher, P.3
-
10
-
-
0242657937
-
A 13.3-Mb/s 0.35 μ m CMOS analog turbo decoder IC with a configurable interleaver
-
Nov.
-
V. C. Gaudet, P. G. Gulak (2003) "A 13.3-Mb/s 0.35 μ m CMOS analog turbo decoder IC with a configurable interleaver", Solid-State Circuits IEEE Journal of, Volume: 38 Issue: 11, Nov. 2003 pp. 2010-2015
-
(2003)
Solid-State Circuits IEEE Journal of
, vol.38
, Issue.11
, pp. 2010-2015
-
-
Gaudet, V.C.1
Gulak, P.G.2
-
11
-
-
0032629092
-
Decoding in analog VLSI
-
April 1999
-
H. A. Loeliger, F. Tarkoy, F. Lustenberger, M. Helfenstein (1999) "Decoding in analog VLSI" Communications Magazine, IEEE, Volume: 37, Issue: 4, April 1999 pp. 99-101
-
(1999)
Communications Magazine, IEEE
, vol.37
, Issue.4
, pp. 99-101
-
-
Loeliger, H.A.1
Tarkoy, F.2
Lustenberger, F.3
Helfenstein, M.4
-
12
-
-
0035246311
-
Probability propagation and decoding in analog VLSI
-
Feb. 2001
-
H. A. Loeliger (2001) "Probability propagation and decoding in analog VLSI", IEEE Trans. Info. Theory, Vol.47, Feb. 2001, pp. 837-843
-
(2001)
IEEE Trans. Info. Theory
, vol.47
, pp. 837-843
-
-
Loeliger, H.A.1
-
13
-
-
0033351808
-
VLSI implementation issues of turbo decoder design for wireless applications
-
20-22 October 1999
-
Z. Wang, H. Suzuki, and K.K. Parhi (1999) "VLSI Implementation Issues of Turbo Decoder Design for Wireless Applications", IEEE Workshop on Signal Processing Systems, 20-22 October 1999, pp. 503-512
-
(1999)
IEEE Workshop on Signal Processing Systems
, pp. 503-512
-
-
Wang, Z.1
Suzuki, H.2
Parhi, K.K.3
-
14
-
-
0035332876
-
Design of fixed-point iterative decoders for concatenated codes with interleavers
-
May 2001
-
G. Montorsi, and S. Benedetto (2001) "Design of Fixed-Point Iterative Decoders for Concatenated Codes with Interleavers" IEEE Jurnal on Selected Areas in Communications, Vol. 19, No. 5, May 2001, pp.871-882
-
(2001)
IEEE Jurnal on Selected Areas in Communications
, vol.19
, Issue.5
, pp. 871-882
-
-
Montorsi, G.1
Benedetto, S.2
-
15
-
-
0024770713
-
An alternative to metric rescaling in Viterbi decoders
-
1989
-
A.P. Hekstra (1989) "An alternative to metric rescaling in Viterbi decoders", IEEE Trans. Commun., Vol. 37, No. 11, pp. 1220-1222, 1989
-
(1989)
IEEE Trans. Commun.
, vol.37
, Issue.11
, pp. 1220-1222
-
-
Hekstra, A.P.1
-
16
-
-
0026981415
-
A 140-Mb/s, 32-State, Radix-4 Viterbi Decoder
-
December 1992
-
P.J. Black, T.H. Meng (1992) "A 140-Mb/s, 32-State, Radix-4 Viterbi Decoder" IEEE Journal of Solid-State Circuits vol. 27, no. 12, December 1992, pp.1877-1885.
-
(1992)
IEEE Journal of Solid-State Circuits
, vol.27
, Issue.12
, pp. 1877-1885
-
-
Black, P.J.1
Meng, T.H.2
-
17
-
-
84890233413
-
An intuitive justification of the MAP decoder for convo-lutional codes
-
February 1998
-
A.J. Viterbi (1998) "An intuitive justification of the MAP decoder for convo-lutional codes", IEEE Journal on Selected Areas in Communications, Vol. 16, No. 2, February 1998.
-
(1998)
IEEE Journal on Selected Areas in Communications
, vol.16
, Issue.2
-
-
Viterbi, A.J.1
-
18
-
-
0035301406
-
Memory optimization of MAP turbo decoder algorithms
-
April 2001
-
C. Schurgers, F. Catthoor, M. Engels (2001) "Memory Optimization of MAP Turbo Decoder ALgorithms", IEEE Trans. on VLSI Systems, Vol. 9, No. 2, April 2001, pp. 305-312
-
(2001)
IEEE Trans. on VLSI Systems
, vol.9
, Issue.2
, pp. 305-312
-
-
Schurgers, C.1
Catthoor, F.2
Engels, M.3
-
19
-
-
0141620329
-
VLSI architectures for SISO-APP decoders
-
August 2003
-
M. Mansour, N. R. Shanbhag (2003) "VLSI Architectures for SISO-APP Decoders", IEEE Tras. on VLSI Systems, Vol. 11, No. 4, August 2003
-
(2003)
IEEE Tras. on VLSI Systems
, vol.11
, Issue.4
-
-
Mansour, M.1
Shanbhag, N.R.2
-
21
-
-
0029516480
-
Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding
-
H. Diwid, H. Meyr (1995) "Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding, " Proc. Personal, Indoor, and Mobile Radio Communications, PIMRC'95, vol. 1, 1995, pp. 193-197
-
(1995)
Proc. Personal, Indoor, and Mobile Radio Communications, PIMRC'95
, vol.1
, Issue.1995
, pp. 193-197
-
-
Diwid, H.1
Meyr, H.2
-
23
-
-
0034515302
-
A High Speed MAP architecture with optimized memory size and power consumption
-
A. Worm, H. Lamm, N. When (2000) "A High Speed MAP architecture with optimized memory size and power consumption, " Proc. IEEE Workshop Signal processing Systems, SiPS 2000, pp. 265-274
-
(2000)
Proc. IEEE Workshop Signal Processing Systems, SiPS 2000
, pp. 265-274
-
-
Worm, A.1
Lamm, H.2
When, N.3
-
24
-
-
0141859010
-
-
A 50 Mbit/s Iterative Turbo-Decoder, March 2000
-
F. Viglione, G. Masera, G. Piccinini, M. Ruo Roch, M. Zamboni (2000) "A 50 Mbit/s Iterative Turbo-Decoder, " Proc. of DATE 2000 Conference, pp. 176-180, March 2000.
-
(2000)
Proc. of DATE 2000 Conference
, pp. 176-180
-
-
Viglione, F.1
Masera, G.2
Piccinini, G.3
Ruo Roch, M.4
Zamboni, M.5
-
25
-
-
0036927792
-
Area-efficient high-speed decoding schemes for turbo decoders
-
December 2002
-
Z. Wang, Z. Chi, K. K. Parhi (2002) "Area-efficient high-speed decoding schemes for turbo decoders, " IEEE Trans. on VLSI Systems, Vol. 10, No. 6, December 2002, pp. 902-912
-
(2002)
IEEE Trans. on VLSI Systems
, vol.10
, Issue.6
, pp. 902-912
-
-
Wang, Z.1
Chi, Z.2
Parhi, K.K.3
-
26
-
-
0033685490
-
Forward computation of backward path metrics for MAP decoders
-
2000
-
Y. Wu, W. J. Ebel, B. D. Woerner (2000) "Forward computation of backward path metrics for MAP decoders, " IEEE VTC, pp. 2257-2261, 2000
-
(2000)
IEEE VTC
, pp. 2257-2261
-
-
Wu, Y.1
Ebel, W.J.2
Woerner, B.D.3
-
27
-
-
84945350386
-
Low power VLSI implementation of the MAP decoder for turbo codes through forward recursive calculation of reverse state metrics
-
17-20 Sept. 2003
-
I. Atluri, T. Arslan (2003) "Low power VLSI implementation of the MAP decoder for turbo codes through forward recursive calculation of reverse state metrics, " IEEE Int. SOC Conf. 17-20 Sept. 2003, pp. 408-411
-
(2003)
IEEE Int. SOC Conf
, pp. 408-411
-
-
Atluri, I.1
Arslan, T.2
-
28
-
-
0037746702
-
Reverse tracing of forward state metric in log-MAP and max-log-MAP decoders
-
25-28 May 2003
-
J. Kwak, S. M. Park, K. Lee (2003) "Reverse tracing of forward state metric in log-MAP and max-log-MAP decoders, " Int. Symp. on Circuits and Systems, 25-28 May 2003
-
(2003)
Int. Symp. on Circuits and Systems
-
-
Kwak, J.1
Park, S.M.2
Lee, K.3
-
29
-
-
0037630985
-
A 24 Mb/s radix-4 LogMAP turbo decoder for 3GPP-HSDPA mobile wireless
-
ISSCC, February 11, 2003, Session 8, paper 8.5
-
M. Bickerstaff, L. davis, C. Thomas, D. Garret, C. Nicol (2003) "A 24 Mb/s radix-4 LogMAP turbo decoder for 3GPP-HSDPA mobile wireless, " International Solid-State Circuits Conference, ISSCC, February 11, 2003, Session 8, paper 8.5
-
(2003)
International Solid-State Circuits Conference
-
-
Bickerstaff, M.1
Davis, L.2
Thomas, C.3
Garret, D.4
Nicol, C.5
-
30
-
-
0032646197
-
VLSI architectures for turbo codes
-
September 1999
-
G. Masera, G. Piccinini, M. Ruo Roch, M. Zamboni (1999) "VLSI architectures for turbo codes", IEEE Trans. on VLSI Systems, Vol.7, No.3, September 1999, pp.369-379
-
(1999)
IEEE Trans. on VLSI Systems
, vol.7
, Issue.3
, pp. 369-379
-
-
Masera, G.1
Piccinini, G.2
Ruo Roch, M.3
Zamboni, M.4
-
31
-
-
0035294983
-
VLSI architectures for iterative decoders in magnetic recording channels
-
Mar. 2001
-
E. Yeo, P. Pakzad, B. Nikolic, V. Anantharam (2001) "VLSI architectures for iterative decoders in magnetic recording channels, " IEEE Trans. Magn., vol. 37, pp. 748-755, Mar. 2001
-
(2001)
IEEE Trans. Magn.
, vol.37
, pp. 748-755
-
-
Yeo, E.1
Pakzad, P.2
Nikolic, B.3
Anantharam, V.4
-
32
-
-
0038073140
-
Performance degradation as a function of overlap depth when using sub-block processing in the decoding of turbo codes
-
1999, Ottawa, Canada
-
A. Hunt, S. Crozier, M. Richards, K. Gracie (1999) "Performance degradation as a function of overlap depth when using sub-block processing in the decoding of turbo codes, " Proc. of IMSC'99, 1999, Ottawa, Canada, pp. 276-280
-
(1999)
Proc. of IMSC'99
, pp. 276-280
-
-
Hunt, A.1
Crozier, S.2
Richards, M.3
Gracie, K.4
-
33
-
-
0036967447
-
A class of power efficient VLSI architectures for high speed turbo-decoding
-
2002, GLOBECOM 2002
-
B. Bougard, A. Giulietti, L. Van der Perre, F. Catthoor (2002) "A class of power efficient VLSI architectures for high speed turbo-decoding, " Global Telecommunications Conference, 2002, GLOBECOM 2002, Vol. 1, pp. 549-553
-
(2002)
Global Telecommunications Conference
, vol.1
, pp. 549-553
-
-
Bougard, B.1
Giulietti, A.2
Perre Der L.Van3
Catthoor, F.4
-
34
-
-
4544340836
-
-
Multiple Slice Turbo Codes, Brest, France, Sept. 2003
-
D. Gnaedig, E. Boutillon, M. Jezequel, V.C. Gaudet, P.G. Gulak (2003) "Multiple Slice Turbo Codes, " Proceedings of the 3rd International Symposium on Turbo Codes and Related Topics, pp 343-346, Brest, France, Sept. 2003
-
(2003)
Proceedings of the 3rd International Symposium on Turbo Codes and Related Topics
, pp. 343-346
-
-
Gnaedig, D.1
Boutillon, E.2
Jezequel, M.3
Gaudet, V.C.4
Gulak, P.G.5
-
35
-
-
0036625313
-
Architectural strategies for low-power VLSI turbo-decoders
-
June 2002
-
G. Masera, M. Mazza, G. Piccinini, F. Viglione, M. Zamboni (2002) "Architectural Strategies for Low-Power VLSI Turbo-Decoders, " IEEE Trans. on VLSI, vol. 10, No. 3, June 2002, pp. 279-285
-
(2002)
IEEE Trans. on VLSI
, vol.10
, Issue.3
, pp. 279-285
-
-
Masera, G.1
Mazza, M.2
Piccinini, G.3
Viglione, F.4
Zamboni, M.5
-
36
-
-
0037186099
-
Parallel turbo coding inter-leavers: Avoiding collisions in accesses to storage elements
-
Feb. 2002
-
A. Giulietti, L. Van der Perre, M. Strum (2002) "Parallel turbo coding inter-leavers: avoiding collisions in accesses to storage elements", Electronics Letters, Vol. 38, Iss. 5, Feb. 2002, pp. 232-234
-
(2002)
Electronics Letters
, vol.38
, Issue.5
, pp. 232-234
-
-
Giulietti, A.1
Perre Der L.Van2
Strum, M.3
-
37
-
-
0037168148
-
Design of dividable interleaver for parallel decoding in turbo codes
-
Oct. 2002
-
J. Kwak, K. Lee (2002) "Design of dividable interleaver for parallel decoding in turbo codes", Electronics Letters, Vol. 38, Iss. 22, Oct. 2002, pp.1362-1364
-
(2002)
Electronics Letters
, vol.38
, Issue.22
, pp. 1362-1364
-
-
Kwak, J.1
Lee, K.2
-
39
-
-
4544349170
-
Inter-window shuffle interleavers for high throughput turbo decoding
-
Brest, France, Sept. 2003
-
A. Nimbalker, T.K. Blankenship, B. Classon, T.E. Fuja, D.J. Costello Jr. (2003) "Inter-Window Shuffle Interleavers for High Throughput Turbo Decoding, " Proceedings of the 3rd International Symposium on Turbo Codes and Related Topics, pp 355-358, Brest, France, Sept. 2003
-
(2003)
Proceedings of the 3rd International Symposium on Turbo Codes and Related Topics
, pp. 355-358
-
-
Nimbalker, A.1
Blankenship, T.K.2
Classon, B.3
Fuja, T.E.4
Costello Jr., D.J.5
-
40
-
-
77955992881
-
-
Technical Report CCIT-TR436, Electrical Engineering, Technion-Israel Institute of Technology, July 2003
-
R. Dobkin, M. Peleg, R. Ginosar (2003) "Parallel VLSI architectures and Parallel Interleaving Design for Low-Latency MAP Turbo Decoders, " Technical Report CCIT-TR436, Electrical Engineering, Technion-Israel Institute of Technology, July 2003
-
(2003)
Parallel VLSI Architectures and Parallel Interleaving Design for Low-Latency MAP Turbo Decoders
-
-
Dobkin, R.1
Peleg, M.2
Ginosar, R.3
-
41
-
-
77956428704
-
Optimized concurrent interleaving architecture for high-throughput turbodecoding
-
M.J. Thul, F. Gilbert, N. Wehn (2002) "Optimized concurrent interleaving architecture for high-throughput turbodecoding, " 9th Int. Conf. On Electronics, Circuits and Systems 2002, vol. 3, pp. 1099-1102
-
(2002)
9th Int. Conf. on Electronics, Circuits and Systems 2002
, vol.3
, pp. 1099-1102
-
-
Thul, M.J.1
Gilbert, F.2
Wehn, N.3
-
42
-
-
84893714166
-
Communication centric architectures for turbo-decoding on embedded multiprocessors
-
F. Gilbert, M.J. Thul, N. Wehn (2002) "Communication centric architectures for turbo-decoding on embedded multiprocessors, " Conference and Exhibition on Design, Automation and Test in Europe 2003, pp. 356-361
-
(2002)
Conference and Exhibition on Design, Automation and Test in Europe 2003
, pp. 356-361
-
-
Gilbert, F.1
Thul, M.J.2
Wehn, N.3
-
43
-
-
0141788601
-
Concurrent Interleaving architectures for high-throughput channel coding
-
M.J. Thul, F. Gilbert, N. Wehn (2003) "Concurrent Interleaving architectures for high-throughput channel coding, " Proceedings of ICASSP 2003, Vol. 2, pp. 613-616
-
(2003)
Proceedings of ICASSP 2003
, vol.2
, pp. 613-616
-
-
Thul, M.J.1
Gilbert, F.2
Wehn, N.3
-
44
-
-
13944263593
-
Scalable and area efficient concurrent interleaver for high throughput turbo-decoders
-
Aug. 31-Sept. 3, 2004
-
F. Speziali, J. Zory (2004) "Scalable and area efficient concurrent interleaver for high throughput turbo-decoders, " Euromicro Symposium on Digital System Design, Aug. 31-Sept. 3, 2004 pp. 334-341
-
(2004)
Euromicro Symposium on Digital System Design
, pp. 334-341
-
-
Speziali, F.1
Zory, J.2
-
45
-
-
5044252274
-
Mapping interleaving laws to parallel Turbo decoder architectures
-
Brest, France, Sept. 2003
-
A. Tarable, G. Montorsi, S. Benedetto (2003) "Mapping interleaving laws to parallel Turbo decoder architectures, " Proceedings of the 3rd International Symposium on Turbo Codes and Related Topics, pp. 153-156, Brest, France, Sept. 2003
-
(2003)
Proceedings of the 3rd International Symposium on Turbo Codes and Related Topics
, pp. 153-156
-
-
Tarable, A.1
Montorsi, G.2
Benedetto, S.3
-
46
-
-
1942424194
-
Mapping interleaving laws to parallel Turbo decoder architectures
-
March 2004
-
A. Tarable, S. Benedetto (2004) "Mapping interleaving laws to parallel Turbo decoder architectures, " IEEE Comm. Letters, Vol. 8, No. 3, March 2004, pp. 162-164
-
(2004)
IEEE Comm. Letters
, vol.8
, Issue.3
, pp. 162-164
-
-
Tarable, A.1
Benedetto, S.2
-
47
-
-
0033282682
-
Performance optimization of VLSI transceiver for low-energy communications systems
-
31 Oct.-3 Nov. 1999
-
A. P. Worthen, S. Hong, R. Gupta, W. E. Stark (1999) "Performance optimization of VLSI transceiver for low-energy communications systems, " Military Communication Conference, MILCOM 1999, Vol. 2, 31 Oct.-3 Nov. 1999, pp. 1434-1438
-
(1999)
Military Communication Conference, MILCOM 1999
, vol.2
, pp. 1434-1438
-
-
Worthen, A.P.1
Hong, S.2
Gupta, R.3
Stark, W.E.4
-
48
-
-
0035242927
-
Reducing power consumption of turbo decoder using adaptive iteration with variable supply voltage
-
Feb. 2001
-
O.Y. Leung, C. Y. Tsui, R. S. Cheng (2001) "Reducing power consumption of turbo decoder using adaptive iteration with variable supply voltage, " IEEE Trans. on VLSI Systems, Vol. 9, No. 1, Feb. 2001, pp. 34-40
-
(2001)
IEEE Trans. on VLSI Systems
, vol.9
, Issue.1
, pp. 34-40
-
-
Leung, O.Y.1
Tsui, C.Y.2
Cheng, R.S.3
-
49
-
-
84890173647
-
-
Adaptive Turbo Decoding for Indoor Wireless Communication, 21-24 September 1999
-
C. Schurgers, L. Van der Perre, M. Engels, H. De Man (1999) "Adaptive Turbo Decoding for Indoor Wireless Communication, " IEEE Wireless Communications and Networking Conference (WCNC), 21-24 September 1999, pp. 1498-1502
-
(1999)
IEEE Wireless Communications and Networking Conference (WCNC
, pp. 1498-1502
-
-
Schurgers, C.1
Perre Der L.Van2
Engels, M.3
De Man, H.4
-
50
-
-
0031212817
-
Supply and threshold voltage scaling for low power CMOS
-
August 1997
-
R. Gonzales, B. M. Gordon, M. A. Horowitz (1997) "Supply and Threshold Voltage Scaling for Low Power CMOS, " IEEE Journal of Solid-State Circuits, vol. 32, no. 8, pp. 1210-1216, August 1997.
-
(1997)
IEEE Journal of Solid-State Circuits
, vol.32
, Issue.8
, pp. 1210-1216
-
-
Gonzales, R.1
Gordon, B.M.2
Horowitz, M.A.3
-
51
-
-
33644564475
-
rd
-
Brest, France, 2003
-
rd Int. Symp. on Turbo Codes and Related Topics, Brest, France, 2003, pp. 511-514
-
(2003)
Int. Symp. on Turbo Codes and Related Topics
, pp. 511-514
-
-
Bougard, B.1
Giulietti, A.2
Desset, C.3
Perre Der L.Van4
Catthoor, F.5
-
52
-
-
84890214387
-
-
www.latticesim.com/products
-
-
-
-
53
-
-
84890138204
-
-
www.xilinx.com/products/logicore/alliance
-
-
-
-
54
-
-
84890195707
-
-
www.altera.com/products/ip
-
-
-
-
55
-
-
84890136568
-
-
www.us.design-reuse.com/sip
-
-
-
-
56
-
-
84890130914
-
-
www.icoding.com/products.htm
-
-
-
-
57
-
-
84890189601
-
-
www.tij.co.jp/jsc/docs/dsps/support/dowload/c6000
-
-
-
-
58
-
-
3042568910
-
Implementation of a UMTS turbo-decoder on a dynamically reconfigurable platform
-
16-20 Feb. 2004, Vol.2
-
A. La Rosa, C. Passerone, F. Gregoretti, L. Lavagno (2004) "Implementation of a UMTS turbo-decoder on a dynamically reconfigurable platform", Design, Automation and Test in Europe, Volume: 2, 16-20 Feb. 2004 pp. 1218-1223 Vol.2
-
(2004)
Design, Automation and Test in Europe
, vol.2
, pp. 1218-1223
-
-
La Rosa, A.1
Passerone, C.2
Gregoretti, F.3
Lavagno, L.4
-
59
-
-
84890167008
-
-
Diploma Thesis, Institute for Integrated Signal Processing Systems, RWTH Aachen
-
P. Salz, O. Schliebusch, D. Kammler, G. Ascheid, R. Leupers, H. Meyr (2004) Specification and Implementation of an Application Specific Instruction Set Processor (ASIP) for Turbo Decoding, Diploma Thesis, Institute for Integrated Signal Processing Systems, RWTH Aachen"
-
(2004)
Specification and Implementation of An Application Specific Instruction Set Processor (ASIP) for Turbo Decoding
-
-
Salz, P.1
Schliebusch, O.2
Kammler, D.3
Ascheid, G.4
Leupers, R.5
Meyr, H.6
-
60
-
-
84983103128
-
A simplified and efficient implementation of FPGA-based turbo decoder
-
9-11 April 2003
-
S. Sharma, S. Attri, F.C. Chauhan (2003) "A simplified and efficient implementation of FPGA-based turbo decoder" Proceedings of the 2003 IEEE International Conference on Performance, Computing, and Communications Conference, 9-11 April 2003 pp. 207-213
-
(2003)
Proceedings of the 2003 IEEE International Conference on Performance, Computing, and Communications Conference
, pp. 207-213
-
-
Sharma, S.1
Attri, S.2
Chauhan, F.C.3
-
61
-
-
0036563869
-
Design and implementation of a turbo decoder for 3G W-CDMA systems" Consumer Electronics
-
May 2002
-
Xiao-Jun Zeng, Zhi-Liang Hong (2002) "Design and implementation of a turbo decoder for 3G W-CDMA systems" Consumer Electronics, IEEE Transactions on, Volume: 48, Issue: 2, May 2002 pp. 284-291
-
(2002)
IEEE Transactions on
, vol.48
, Issue.2
, pp. 284-291
-
-
Zeng, X.1
Hong, Z.2
-
62
-
-
0035573962
-
FPGA implementation of a 3GPP turbo codec
-
4-7 Nov. 2001, vol.1
-
J. Steensma, C. Dick (2001) "FPGA implementation of a 3GPP turbo codec, " Thirty-Fifth Asilomar Conference on Signals, Systems and Computers, Volume: 1, 4-7 Nov. 2001, pp. 61-65 vol.1
-
(2001)
Thirty-Fifth Asilomar Conference on Signals, Systems and Computers
, vol.1
, pp. 61-65
-
-
Steensma, J.1
Dick, C.2
-
63
-
-
84890146638
-
A Generic 350 Mb/s Turbo-Codec Based on a 16-states SISO Decoder
-
ISSCC, February 18, 2004, Session 23, paper 23.4
-
P. Urard et al. (2004) "A Generic 350 Mb/s Turbo-Codec Based on a 16-states SISO Decoder, " International Solid-State Circuits Conference, ISSCC, February 18, 2004, Session 23, paper 23.4
-
(2004)
International Solid-State Circuits Conference
-
-
Urard, P.1
-
64
-
-
0038306550
-
A Programmable Turbo Decoder for Multiple 3G Wireless Standards
-
ISSCC, February 11, 2003, Session 8, paper 8.7
-
Myoung-Cheol Shin, In-Cheol Park (2003) "A Programmable Turbo Decoder for Multiple 3G Wireless Standards, " International Solid-State Circuits Conference, ISSCC, February 11, 2003, Session 8, paper 8.7
-
(2003)
International Solid-State Circuits Conference
-
-
Shin, M.1
Park, I.2
-
65
-
-
84890168192
-
-
A Scalable 8.7 nJ/bit 75.6 Mb/s Parallel Concatenated Convolutional (Turbo-) CODEC, ISSCC, February 11, 2003, Session 8, paper 8.6
-
B. Bougard et al. (2003) "A Scalable 8.7 nJ/bit 75.6 Mb/s Parallel Concatenated Convolutional (Turbo-) CODEC, " International Solid-State Circuits Conference, ISSCC, February 11, 2003, Session 8, paper 8.6
-
(2003)
International Solid-State Circuits Conference
-
-
Bougard, B.1
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