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Volumn 2, Issue , 2006, Pages 2353-2358

Exploring parallel processing levels for convolutional turbo decoding

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; CONVOLUTION; DECODING; DIGITAL COMMUNICATION SYSTEMS; ERROR CORRECTION; ITERATIVE METHODS; MESSAGE PASSING; TURBO CODES;

EID: 84961944273     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICTTA.2006.1684774     Document Type: Conference Paper
Times cited : (34)

References (15)
  • 2
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    • Good error-correcting codes based on very sparse matrices
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    • D. J. C. MacKay, "Good error-correcting codes based on very sparse matrices, " IEEE Trans. Inf. Theory, vol. 45, pp. 399-431, Mar. 1999.
    • (1999) IEEE Trans. Inf. Theory , vol.45 , pp. 399-431
    • MacKay, D.J.C.1
  • 3
    • 0016037512 scopus 로고
    • Optimal decoding of linear codes for minimizing symbol error rate
    • Mar
    • L. Bahl, J. Cocke, F. Jelinek, and J. Raviv, "Optimal decoding of linear codes for minimizing symbol error rate, " IEEE Trans. Inf. Theory, vol. IT-20, pp. 284-287, Mar. 1974.
    • (1974) IEEE Trans. Inf. Theory , vol.IT-20 , pp. 284-287
    • Bahl, L.1    Cocke, J.2    Jelinek, F.3    Raviv, J.4
  • 5
    • 0037311818 scopus 로고    scopus 로고
    • VLSI architectures for the MAP algorithm
    • Feb
    • E. Boutillon, W. J. Gross, and P. G. Gulak, "VLSI architectures for the MAP algorithm, " IEEE Trans. Commun., vol. 51, pp. 175-185, Feb. 2003.
    • (2003) IEEE Trans. Commun , vol.51 , pp. 175-185
    • Boutillon, E.1    Gross, W.J.2    Gulak, P.G.3
  • 6
    • 0035301406 scopus 로고    scopus 로고
    • Memory optimization of MAP turbo decoder algorithms
    • Apr
    • C. Schurgers, F. Catthoor, and M. Engels, "Memory optimization of MAP turbo decoder algorithms, " IEEE Trans. VLSI Syst., vol. 9, pp. 305-312, Apr. 2001.
    • (2001) IEEE Trans. VLSI Syst , vol.9 , pp. 305-312
    • Schurgers, C.1    Catthoor, F.2    Engels, M.3
  • 9
    • 0141744886 scopus 로고    scopus 로고
    • An efficient architecture for high speed turbo decoders
    • April
    • A. Abbasfar, and K. Yao, "An Efficient Architecture for High Speed Turbo Decoders, " Proc. of ICASSP 2003, pp. IV521-IV524, April 2003.
    • (2003) Proc. of ICASSP 2003 , pp. IV521-IV524
    • Abbasfar, A.1    Yao, K.2
  • 12
    • 84893714166 scopus 로고    scopus 로고
    • Communication centric architectures for turbo-decoding on embedded multiprocessors
    • Munich
    • F. Gilbert, M. Thul and N. Wehn. "Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors", Proceedings of DATE 2003, Munich.
    • (2003) Proceedings of DATE
    • Gilbert, F.1    Thul, M.2    Wehn, N.3
  • 15
    • 0000035405 scopus 로고    scopus 로고
    • Optimal and sub-optimal maximum a posteriori algorithms suitable for turbo decoding
    • P. Robertson, P. Hoeher, and E. Villebrun, "Optimal and Sub-Optimal Maximum a Posteriori Algorithms Suitable for Turbo Decoding, " European Transactions on Telecommunications (ETT), vol. 8, no. 2, 1997, pp. 119- 125.
    • (1997) European Transactions on Telecommunications (ETT) , vol.8 , Issue.2 , pp. 119-125
    • Robertson, P.1    Hoeher, P.2    Villebrun, E.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.