Mechanical stress aware optimization for leakage power reduction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 5, 2010, Pages 722-736

  Joshi, Vivek ^a   Cline, Brian ^b   Sylvester, Dennis ^a   Blaauw, David ^a   Agarwal, Kanak ^c  

^a UNIVERSITY OF MICHIGAN   (United States)

^b Research and Development Group   (United States)

^c IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

Layout; Leakage; Mobility; Performance; Stress

Indexed keywords

ACTIVE AREA; BENCHMARK CIRCUIT; DRIVE CURRENTS; DUAL-VTH; INDUSTRIAL PROCESSS; JOINT OPTIMIZATION; LAYOUT; LEAKAGE POWER REDUCTION; MECHANICAL STRESS; MOBILITY ENHANCEMENT; MOBILITY PERFORMANCE; OPTIMAL POWER; OPTIMIZATION ALGORITHMS; OPTIMIZATION TECHNIQUES; PERFORMANCE ENHANCEMENTS; PERFORMANCE TRADE-OFF; SIMULATION RESULT; SMALL AREA; STANDARD CELL; STRESS ASSIGNMENT; STRESS ENHANCEMENT;

DELAY CIRCUITS; ELECTRIC BATTERIES; LEAKAGE CURRENTS; MECHANICAL PROPERTIES; OPTIMIZATION; STANDARDS;

STRESSES;

EID: 77951672567     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2042893     Document Type: Article

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