Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 1075-1077

  Yang, H S ^a   Malik, R ^a   Narasimha, S ^a   Li, Y ^a   Divakaruni, R ^a   Agnello, P ^a   Allen, S ^a   Antreasyan, A ^a   Arnold, J C ^a   Bandy, K ^a   Belyansky, M ^a   Bonnoit, A ^a   Bronner, G ^a   Chen, V ^a   Chen, X ^a   Chen, Z ^a   Chidambarrao, D ^a   Chou, A ^a   Clark, W ^a   Crowder, S W ^a   Engel, B ^a   Harifuchi, H ^a   Huang, S F ^a   Jagannathan, R ^a   Jamin, F F ^a   Kohyama, Y ^a   Kuroda, H ^a   Lai, C W ^a   Lee, H K ^a   Lee, W H ^a   Lim, E H ^a   Lai, W ^a   Mallikarjunan, A ^a   Matsumoto, K ^a   McKnight, A ^a   Nayak, J ^a   Ng, H Y ^a   Panda, S ^a   Rengarajan, R ^a   Steigerwalt, M ^a   Subbanna, S ^a   Subramanian, K ^a   Sudijono, J ^a   Sudo, G ^a   Sun, S P ^a   Tessier, B ^a   Toyoshima, Y ^a   Tran, P ^a   Wise, R ^a   Wong, R ^a   Yang, I Y ^a   Wann, C H ^a   Su, L T ^a   Horstmann, M ^b   Feudel, Th ^b   Wei, A ^b   Frohberg, K ^b   Burbach, G ^b   Gerhardt, M ^b   Lenski, M ^b   Stephan, R ^b   Wieczorek, K ^b   Schaller, M ^b   Salz, H ^b   Hohage, J ^b   Ruelke, H ^b   Klais, J ^b   Huebler, P ^b   Luning, S ^b   Van Bentum, R ^b   Grasshoff, G ^b   Schwan, C ^b   Ehrichs, E ^b   Goad, S ^b   Buller, J ^b   Krishnan, S ^b   Greenlaw, D ^b   Raab, M ^b   Kepler, N ^b   more..

^a IBM RESEARCH   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP POWER; DUAL STRESS LINERS (DSL); GATE LENGTH; PERFORMANCE ENHANCEMENT; CMOS FLOW; CMOS MANUFACTURING; DRIVE CURRENT ENHANCEMENT; DUAL STRESS LINERS; GATE-LENGTH; HIGH-PERFORMANCE CMOS; INVERTER RINGS; MOBILITY ENHANCEMENT; PERFORMANCE; RING OSCILLATOR;

COMPRESSIVE STRESS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC INVERTERS; EPITAXIAL GROWTH; FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR); MICROPROCESSOR CHIPS; OPTIMIZATION; RANDOM ACCESS STORAGE; SILICON NITRIDE; SILICON ON INSULATOR TECHNOLOGY; STRESS ANALYSIS; CMOS INTEGRATED CIRCUITS; DIGITAL SUBSCRIBER LINES;

CMOS INTEGRATED CIRCUITS; HOLE MOBILITY;

EID: 21644452652     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. S. Ito et al., IEDM 2000, p. 247.
2. D. Greenlaw et al., IEDM 2003, p. 277.
3. D. Edelstein et al., IITC 2004, p. 214.
4. M. H. Na et al., IEDM 2002, p. 121.
5. T. Ghani et al., IEDM 2003, p. 978.