Management of power and performance with stress memorization technique for 45nm CMOS

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 218-219

  Eiho, A ^a   Sanuki, T ^a   Morifuji, E ^a   Iwamoto, T ^b   Sudo, G ^a   Fukasaku, K ^c   Ota, K ^c   Sawada, T ^a   Fuji, O ^a   Nii, H ^a   Togo, M ^b   Ohno, K ^c   Yoshida, K ^a   Tsuda, H ^b   Ito, T ^a   Shiozaki, Y ^a   Fuji, N ^a   Yamazaki, H ^a   Nakazawa, M ^c   Iwasa, S ^a   Muramatsu, S ^b   Nagaoka, K ^c   Iwai, M ^a   Ikeda, M ^b   Saito, M ^c   Naruse, H ^a   Enomoto, Y ^c   Kitano, ^b   Yamada, S ^a   Imai, K ^b   Nagashima, N ^c   Kuwata, T ^b   Matsuoka, F ^a   more..

^a Advanced Logic Technology Dept   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

^c SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

MOSFET DEVICES; SPEECH TRANSMISSION; STRESS CONCENTRATION; SURFACE MOUNT TECHNOLOGY;

45 NM TECHNOLOGY; GATE LEAKAGES; IN CHANNELS; MOBILITY ENHANCEMENT; POWER REDUCTIONS; SCALED CMOS; STRESS CHANGES; STRESS DISTRIBUTIONS; VLSI TECHNOLOGIES;

TECHNOLOGY;

EID: 47249101504     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339699     Document Type: Conference Paper

References (4)

1. H.Nii,IEDM.Tech.Dig., p.685, 2006
2. K.Ohta, IEDM.Tech.Dig.p.27, 2002
3. C.Ortolland, VLSI Symp., p.96, 2006
4. S.Thompson, T-ED, p. 1010, 2006