The impact of layout on stress-enhanced transistor performance

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn 2005, Issue , 2005, Pages 143-146

  Moroz, V ^a   Eneman, G ^b,c,d   Verheyen, P ^b   Nouri, F ^e   Washington, L ^e   Smith, L ^a   Jurczak, M ^b   Pramanik, D ^a   Xu, X ^a  

^a SYNOPSYS INC   (United States)

^b CMOS Device Research Group   (Belgium)

^c UNIVERSITY OF LEUVEN   (Belgium)

^d FUND FOR SCIENTIFIC RESEARCH   (Belgium)

^e APPLIED MATERIALS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENTS; HOLE MOBILITY; INTEGRATED CIRCUIT LAYOUT; SILICON ALLOYS; STRESS ANALYSIS;

MOBILITY MODELS; STRESS TRANSFER;

TRANSISTORS;

EID: 33745709140     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/sispad.2005.201493     Document Type: Conference Paper

References (7)

1. R. A. Bianchi et al, IEDM Tech. Dig., p. 117-120. (2002).
2. S. E. Thompson et al, IEEE Electron Dev. Lett., 25, n.4, p.191-193, (2004).
3. P. R. Chidambaram et al, VLSI Symp. Tech. Dig., p. 48-49, (2004).
4. F. Nouri et al, IEDM Tech. Dig., p. 1055-1058, (2004).
5. G. Eneman et al, VLSI Symp. Tech. Dig., p. 22-23, (2005).
6. V. Moroz et al, Materials Science in Semicond. Processing, 6, p.27-36, (2003).
7. L. Smith et al, IEEE Electron Dev. Lett., to be published.