Chip optimization through STI-stress-aware placement perturbations and fill insertion

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 7, 2008, Pages 1241-1252

  Kahng, Andrew B ^a,b   Sharma, Puneet ^a,c,d   Topaloglu, Rasit Onur ^a,b,e  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d FREESCALE SEMICONDUCTOR INC   (United States)

^e ADVANCED MICRO DEVICES   (United States)

Author keywords

Design for manufacturing (DFM); Performance analysis and optimization; Shallow trench isolation (STI); Stress modeling and optimization

Indexed keywords

COMPUTER SIMULATION; ELECTRIC BATTERIES; INTEGRATED CIRCUITS; MOSFET DEVICES; NETWORKS (CIRCUITS); OPTIMIZATION; PERTURBATION TECHNIQUES; SEMICONDUCTING SILICON; SPEECH ANALYSIS; STANDARDS; TIME MEASUREMENT;

(ABIOTIC AND BIOTIC) STRESS; (OTDR) TECHNOLOGY; 65-NM NODES; CIRCUIT PERFORMANCES; CLOCK FREQUENCIES; COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS); CRITICAL PATHS; DELAY ANALYSIS; IMPACT MODELING; INTRINSIC STRESSES; PERFORMANCE IMPROVEMENTS; PROCESS SIMULATIONS; PRODUCTION CELLS; SHALLOW TRENCH ISOLATION (STI); SIMULATION PROGRAMS; STANDARD CELL DESIGNS; STRESS ENGINEERING; SYNTHESIS (OF CHIRAL IONIC LIQUIDS); TIMING ANALYSIS; TIMING DRIVEN; WIRE LENGTHS; WORST CASE ANALYSIS;

SPICE;

EID: 45849123251     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.923083     Document Type: Article

References (31)

1. Cadence SoC Encounter. [Online]. Available: http://www.cadence. com/products/digital_ic/soc_encounter/index.aspx
2. Synopsys Design Compiler. [Online]. Available: http://www.synopsys.com/products/logic/design_compiler.html
3. Synopsys HSPICE. [Online]. Available: http://www.synopsys.com/ products/mixedsignal/hspice/hspice.html
4. OpenAccess API. [Online]. Available: http://openeda.si2.org
5. Synopsys PrimeTime. [Online]. Available: http://www.synopsys.com/ products/analysis/primetime_ds.html
6. A. B. Kahng, P. Sharma, and R. O. Topaloglu, "Exploiting STI stress for performance," in Proc. ICCAD, 2007, pp. 83-90.
7. H. A. Rueda, "Modeling of mechanical stress in silicon isolation technology and its influence on device characteristics," Ph.D. dissertation, Univ. Florida, Gainesville, FL, 1999.
8. C. S. Smith, "Piezoresistance effect in germanium and silicon," Phys. Rev., vol. 94, no. 1, pp. 42-49, Apr. 1954.
9. S. W. Chung et al., "Novel shallow trench isolation process using flowable oxide CVD for sub-100 nm DRAM," in Proc. IEDM, 2002, pp. 233-236.
10. J.-P. Han et al., "Novel enhanced stressor with graded embedded SiGe source/drain for high performance CMOS devices," in Proc. IEDM, 2006, pp. 1-4.
11. Q. Ouyang et al., "Characteristics of high performance PFETs with embedded SiGe source/drain and (100) channels on 45° rotated wafers," in Proc. Int. Symp. VLSI Technol., 2005, pp. 27-28.
12. Y. Tateshita et al., "High-performance and low-power CMOS device technologies featuring metal/high-k gate stacks with uniaxial strained silicon channels on (100) and (110) substrates," in Proc. IEDM, 2006, pp. 1-4.
13. Q. Ouyang et al., "Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates," in Proc. Symp. VLSI Technol., 2005, pp. 28-29.
14. M. Yang et al., "Hybrid-orientation technology (HOT): Opportunities and challenges," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 965-978, May 2006.
15. W.-H. Lee et al., "High performance 65 nm. SOI technology with enhanced transistor strain and advanced-low-K BEOL," in Proc. IEDM, 2005, pp. 61-64.
16. H. S. Yang et al., "Dual stress liner for high performance sub-45 nm gate length SOI CMOS manufacturing," in Proc. IEDM, 2004, pp. 1075-1077.
17. C Ortolland, "Stress memorization technique (SMT) optimization for 45 nm CMOS," in Proc. Symp. VLSI Technol., 2006, pp. 78-79.
18. C.-H. Chen et al., "Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65 nm high-performance strained-Si device application," in Proc. Symp. VLSI Technol., 2004, pp. 56-57.
19. N. Elbel, Z. Gataric, W. Langheinrich, and B. Neureither, "A new STT process based on selective oxide deposition," in Proc. Symp. VLSI Technol. Dig. Tech. Papers, 1998, pp. 208-209.
20. H. S. Lee et al., "An optimized densification of the filled oxide for quarter micron shallow trench isolation (STI)," in Proc. Symp. VLSI Technol. Dig. Tech. Papers, 1996, pp. 158-159.
21. Y.-M. Sheu et al., "Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs," IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 30-38, Jan. 2005.
22. C. Gallon et al., "Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress," IEEE Trans. Electron Devices, vol. 51, no. 8, pp. 1254-1261, Aug. 2004.
23. A. T. Bradley, R. C. Jaeger, J. C. Suhling, and K. J. O'Connor, "Piezoresistive characteristics of short-channel MOSFETs on (100) silicon," IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 2009-2015, Sep. 2001.
24. K.-W. Su et al., "A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics," in Proc. IEEE Custom Integr. Circuits Conf., 2003, pp. 245-248.
25. V. Moroz et al., "The impact of layout on stress-enhanced transistor performance," in Proc. Int. Conf. Simul Semicond. Processes Devices, 2005, pp. 143-146.
26. L. Smith, "TCAD modeling of strain-engineered MOSFETs," in Proc. Mater. Res. Soc. Symp., 2006, vol. 913. Paper ID 0913-D05-05.
27. V. Moroz, L. Smith, X.-W. Lin, D. Pramanik, and G. Rollins, "Stressaware design methodology," in Proc. Int. Symp. Quality Electron, Des., 2006, pp. 807-812.
28. Y.-M. Sheu et al., "Modeling well edge proximity effect on highlyscaled MOSFETs," in Proc. IEEE Custom Integr. Circuits Conf., 2005, pp. 831-834.
29. M. Miyamoto, H. Ohta, Y. Kumagai, Y. Sonobe, K. Ishibashi, and Y. Tainaka, "Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics," IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 440-443, Mar. 2004.
30. H. Tsuno et al., "Advanced analysis and modeling of MOSFET characteristic fluctuation caused by layout variation," in Proc. Symp. VLSI Technol., 2007, pp. 204-205.
31. R. Arghavani et al., "Stress management in sub-90-nm transistor architecture," IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1740-1744, Oct. 2004.