Stress aware layout optimization

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2008, Pages 168-174

  Joshi, Vivek ^a   Cline, Brian ^a   Sylvester, Dennis ^a   Blaauw, David ^a   Agarwal, Kanak ^b  

^a UNIVERSITY OF MICHIGAN   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

Performance

Indexed keywords

NITRIDE STRESS LINERS; STRESS AWARE LAYOUT OPTIMIZATION;

INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; RELIABILITY ANALYSIS; TECHNOLOGY TRANSFER;

CMOS INTEGRATED CIRCUITS;

EID: 43349094030     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1353629.1353666     Document Type: Conference Paper

References (14)