A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 245-248

  Su, Ke Wei ^a   Sheu, Yi Ming ^a   Lin, Chung Kai ^a   Yang, Sheng Jier ^a   Liang, Wen Jya ^a   Xi, Xuemei ^b   Chiang, Chung Shi ^a   Her, Jaw Kang ^a   Chia, Yu Tai ^a   Diaz, Carlos H ^a   Hu, Chenming ^b  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; MOS DEVICES; SEMICONDUCTOR DEVICE MODELS; STRESSES; THRESHOLD VOLTAGE; VELOCITY;

CIRCUIT DESIGN; MECHANICAL STRESS EFFECT; SHALLOW TRENCH ISOLATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0242696135     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. R.A.Bianchi, G.Bouche and O.Roux-dit-Buisson, "Accurate Modeling of Trench Isolation Induced Mechanical Stress Effect on MOSFET Electrical Performance," IEDM 2002, pp. 117-120.
3. M.V.Fishetti and S.E.Laux, "Band Structure, Deformation Potentials and Carrier Mobility in Strained Si, Ge, and SiGe Alloys," JAP, Vol. 80(4), pp.2234-2252, 15 Aug. 1996.
4. A.Lochtefeld and D.A.Antoniadis, "Investigating The Relationship Between Electron Mobility and Velocity in Deeply Scaled NMOS via Mechanical Stress," IEEE TED, Vol.22, No.12, pp.591-593, Dec.2001.
5. H.Park, K.S.Jones, J.A.Slinkman and M.E.Law, "The Effects of Strain on Dopant Diffusion in Silicon," IEDM 1993, pp.303-306.
6. C.-Y.Lu and J.M.Sung, "Reverse Short-Channel Effects on Threshold Voltage in Semicrometer Salicide Devices," IEEE EDL, Vol.10, No.10, pp. 446-448, Oct. 1989.