Novel locally strained channel technique for high performance 55 nm CMOS

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 27-30

  Ota, K ^a   Sugihara, K ^a   Sayama, H ^a   Uchida, T ^a   Oda, H ^a   Eimori, T ^a   Morimoto, H ^a   Inoue, Y ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; COMPRESSIVE STRESS; ELECTRODES; POLYSILICON; RESIDUAL STRESSES; STRAIN; TENSILE STRESS;

LOCAL STRAINED CHANNELS (LSC);

CMOS INTEGRATED CIRCUITS;

EID: 0036923437     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. J. J. Welser, et al., IEDM Tech. Dig., p1000, 1992
2. C. K. Maiti, et al., Semicond. Sci. Technol., vol. 13, p1225, 1998
3. T. Mizuno, et al., IEEE Trans. Elec. Devices, Vol. 48, p.1612, 2001.
4. F. Ootsuka et al., IEDM Tech. Dig., p.575, 2000.
5. S. Ito et al., IEDM Tech. Dig., p.247, 2000.
6. A. Shimizu et al. IEDM Tech. Dig., p433, 2001.
7. H. S. Momose et al., IEDM Tech. Dig., p.65, 1990.