Layout-aware compact model of MOSFET characteristics vriations induced by STI stress

IEICE Transactions on Electronics

Volumn E91-C, Issue 7, 2008, Pages 1142-1150

  Yamada, Kenta ^a,b   Sato, Takashi ^b   Amakawa, Shuhei ^b   Nakayama, Noriaki ^b   Masu, Kazuya ^b   Kumashiro, Shigetaka ^c  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^c MIRAI Selete   (Japan)

Author keywords

Layput aware; Modeling; SPICE; STI; Stress

Indexed keywords

CIRCUIT SIMULATION; GEOMETRY; MODELS; MOSFET DEVICES; SPICE; STRESSES; THRESHOLD VOLTAGE;

65 NM CMOS TECHNOLOGIES; CHANNEL ORIENTATIONS; DEVICE CHARACTERISTICS; LAYOUT DEPENDENTS; LAYPUT-AWARE; POST LAYOUT SIMULATION; SATURATION CURRENT; SHALLOW TRENCH ISOLATION;

SEMICONDUCTING SILICON;

EID: 68349151645     PISSN: 09168524     EISSN: 17451353     Source Type: Journal    
DOI: 10.1093/ietele/e91-c.7.1142     Document Type: Article

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