Leakage power reduction using stress-enhanced layouts

Proceedings - Design Automation Conference

Volumn , Issue , 2008, Pages 912-917

  Joshi, Vivek ^a   Cline, Brian ^a   Sylvester, Dennis ^a   Blaauw, David ^a   Agarwal, Kanak ^b  

^a UNIVERSITY OF MICHIGAN   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

Layout; Leakage; Mobility; Performance; Stress

Indexed keywords

LAYOUT; LEAKAGE; MOBILITY; PERFORMANCE; STRESS;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; INDUSTRIAL ENGINEERING;

STRESSES;

EID: 51549105139     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555950     Document Type: Conference Paper

References (22)

1. F. Andrieu et al., "Experimental and Comparative Investigation of Low and High Field Transport in Substrate- and Process-Induced Strained Nanoscale MOSFETs," in Proc. VLSI Tech. Symp. Tech. Dig., pp. 176-177, 2005.
2. K. Mistry et al., "Delaying Forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology," in Proc. VLSI Technol. Symp. Tech. Dig., pp. 50-51,2005.
3. S. Wolf, "Silicon Processing for the VLSI Era," Lattice Press, 1995.
4. A. Chandrakasan et al., "Design of High-Performance Microprocessor Circuits," in IEEE press, 2001.
5. t Circuits," IEEE Trans. on VLSI Systems, Vol. 10, No. 2, pp. 79-90, April 2002.
6. L. Wei et al., "Design and optimization of low voltage high performance dual threshold CMOS circuits," in Proc. 35th Design Automation Conference, pp. 489-494, 1998.
7. D. Sylvester and A. Srivastava, "Computer-Aided Design for Low-Power Robust Computing in Nanoscale CMOS,", in Proc. of the IEEE, Vol. 95, pp. 507-529, March 2007.
8. R. A. Bianchi et al., "Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance," in Proc. IEDM,pp. 117-120,2002.
9. A. Kahng et al., "Exploiting STI Stress for Performance," in Proc. ICCAD, November 2007.
10. V. Moroz et al., "The Impact of Layout on Stress-Enhanced Transistor Performance," in Proc. SISPAD, pp. 143-146, 2005.
11. M. V. Dunga et al., "Modeling Advanced FET Technology in a Compact Model," in IEEE Trans. on Elect. Dev., Vol. 53, No. 9, pp. 1971-1978, September 2006.
12. V. Joshi et al., "Stress Aware Layout Optimization," in Proc. ISPD 2008, to appear April 2008.
13. V. Chan et al., "Strain for PMOS performance Improvement," in Proc. CICC, pp. 667-674, 2005.
14. W. H. Lee et al., "High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL," in Proc. IEDM, 2005.
15. H. S. Yang et al., "Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing," in Proc. IEDM, pp. 1075-1077, 204.
16. K. Ota et al., "Novel locally strained channel technique for high performance 55nm CMOS," in Proc. IEDM, pp. 27-30, 2002.
17. Z. Luo et al., "Design of high performance PFETs with strained si channel and laser anneal," in Proc. IEDM, pp. 489-492, 2005.
18. Manual, Davinci 3D TCAD, Version 2005.10.
19. Manual, Synopsys TSUPREM4, Version 2007.03.
20. A. Dharchoudhury et al., "Transistor-level sizing and timing verification of domino circuits in the powerPC™ microprocessor," in Proc. ICCD, pp. 143-148, Oct. 1997.
21. V. Zyuban et al., "Unified Methodology for Resolving Power-Performance Tradeoffs at the Microarchitectural and Circuit Levels," in Proc. ISLPED, pp. 166-171, August 2002.
22. S. Burns et al., "Comparative Analysis of Conventional and Statistical Design Techniques," in Proc. 44th Design Automation Conference, pp 238-243, June 2007.